Proposal Explorer

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In production

• R3 Model identity attestation for showing users that a service runs the declared model weights

Built for an adversarial prover

Side-channel suppression for isolated facilities and Hardware-enabled guarantees (flexHEG) and guarantee processors

No new hardware needed

Model identity attestation

Flaws since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Model identity attestation ^{4 16}

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Side-channel suppression for isolated facilities, Low-trust AI compute verification system overview: Analysis
• Model identity attestation: Independent red-team
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis

Open critical flaws

• Underlying attestation can be forged or relayed in Model identity attestation

  Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{5 7 11 13 14 15}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. In the proposal.

Family findings

• Side-channel suppression for isolated facilities

  Context for Low-trust AI compute verification system overview. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

    Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ³

    Theoretical argument · Significant · Open. On the record

  • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

    Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ³

    Theoretical argument · Significant · Open. On the record

  • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

    The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ³

    Open question · Significant · Open. On the record

Open significant flaws

10 flaws in 3 mechanisms

• Mismatches cannot be attributed to cheating or error in Low-trust AI compute verification system overview

  A failed hash or replay does not show whether it came from an evasion attempt, a random bit flip or an evaluation error. The author notes that if detected anomalies can plausibly be waved off as malfunctions, deterrence becomes less effective, so the parties need an agreed escalation procedure that ends in attribution. ¹

  Theoretical argument · Significant · Open. On the record

• Inspector agents may be manipulable in Low-trust AI compute verification system overview

  Automated compliance screening with LLM-based inspector agents must resist prompt-injection attacks. Adversarially trained systems might hide malicious actions with steganography, which makes backdoor detection an open problem. ¹

  Open question · Significant · Open. On the record

• For private models, a user can confirm consistency but not content in Model identity attestation

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{4 17}

  Open question · Significant · Open. On the record

• Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation

  The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. ^{6 12}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. Add

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{19 21}

  Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ¹⁹

  Theoretical argument · Significant · Open. On the record

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{18 20}

  Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ¹⁹

  Theoretical argument · Significant · Open. On the record

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{19 20}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this flaw is mitigated. Add

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{18 20}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R1 Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws

1 mechanism with minor findings

• Deliberate faults leak a bit each in Low-trust AI compute verification system overview

  A malicious device can leak one bit by deliberately outputting a wrong result, which blocks a disclosure when the cross-comparison fails. The design therefore needs a pre-agreed budget of tolerated faults. ¹

  Theoretical argument · Minor · Open. On the record

Not yet demonstrated

R1 Side-channel suppression for isolated facilities and R1 Hardware-enabled guarantees (flexHEG) and guarantee processors

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 Deterministic and bit-exact inference Add
  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Bit-exact inference would remove the numerical tolerance that leaves this channel.
  • Side-channel suppression for isolated facilities waits on it. Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question.
  • Model identity attestation waits on it. Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling.
• R1 Chip registries and manufacturing records Add
  • Bears on the open significant flaw “Supply-chain diversion and hidden backdoors” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
• R1 Network taps and certifiers Add
  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.
  • Side-channel suppression for isolated facilities waits on it. Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question.
• R1 Remote detection of data centres Add
  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
• R3 TEE remote attestation for AI workloads Add
  • Model identity attestation waits on it. Attestation that resists physical attackers, for the enclave variant.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
• R2 Tamper evidence for verifier devices Add
  • Side-channel suppression for isolated facilities waits on it. Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
• R2 Timed challenge-response and memory-occupation challenges Add
  • Side-channel suppression for isolated facilities waits on it. Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open.

Missing prerequisites

• R1 Network taps and certifiers needed by Side-channel suppression for isolated facilities Add
• R3 Deterministic and bit-exact inference needed by Side-channel suppression for isolated facilities Add
• R3 TEE remote attestation for AI workloads needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add
• R1 Chip registries and manufacturing records needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add

Shared foundations

• Deterministic and bit-exact inference relied on by Side-channel suppression for isolated facilities and Model identity attestation
• Tamper evidence for verifier devices relied on by Side-channel suppression for isolated facilities and Hardware-enabled guarantees (flexHEG) and guarantee processors
• TEE remote attestation for AI workloads relied on by Model identity attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors

Blockers

14 blockers recorded

• Side-channel suppression for isolated facilities
  • Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question. Performance & compatibility. Waits on Network taps and certifiers ¹
  • Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question. Performance & compatibility. Waits on Deterministic and bit-exact inference ¹
  • Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging. Hardware trust. Waits on Tamper evidence for verifier devices ¹
  • A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹
  • Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ¹
  • The threat model is under-developed and needs input from cybersecurity and AI threat-modelling experts. Adversarial validation ¹
• Model identity attestation
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹¹
  • Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. Protocol soundness. Waits on Deterministic and bit-exact inference ⁶
  • The recomputation variant needs the verifier to hold the declared weights. Access & governance ⁶
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ¹⁹
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{19 21}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{18 20}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ¹⁸
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ²⁰

From the family or selected implementation's record. ?

Model weights

Depends on the design for Model identity attestation.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Depends on the design for Model identity attestation.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Training data

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Model identity attestation.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Side-channel suppression for isolated facilities

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Model identity attestation

• R2 Attestable Audits Research prototype, University of Cambridge
• R2 PAL*M Research prototype, University of Waterloo
• R3 Tinfoil model identity (Modelwrap) Product, Tinfoil

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

1. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
2. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
3. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
4. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
5. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
6. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
7. A primer on secure enclaves, Tinfoil (2026). Original
8. Backend infrastructure, Tinfoil (2026). Original
9. How verification works in Tinfoil, Tinfoil (2026). Original
10. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
11. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
12. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
13. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
14. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
15. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
16. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
17. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
18. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
19. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
20. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
21. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
22. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
23. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original