Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Hardware-attested weight binding for hardware-attested weight binding showing users that a service runs its committed weights

No new hardware needed

Hardware-attested weight binding and Chip registries and manufacturing records

Failures since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Hardware-attested weight binding ^{1 11}

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Hardware-attested weight binding: Independent red-team
• Chip registries and manufacturing records: Analysis

Open critical failures

• Underlying attestation can be forged or relayed in Hardware-attested weight binding

  Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{2 3 7 8 9 10}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Open significant failures

1 failure in 1 mechanism

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ¹⁴

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• For private models, a user can confirm consistency but not content in Hardware-attested weight binding

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{1 12}

  Scope limitation · Open question. On the record

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{15 17}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ¹⁵

  Scope limitation · Theoretical argument. On the record

Not yet demonstrated

Proposed Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
• Operational use TEE remote attestation for AI workloads Add
  • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Hardware-attested weight binding Add

Blockers

4 blockers recorded

• Hardware-attested weight binding
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ⁷
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{13 14}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{13 14 15}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{15 17}

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-attested weight binding.

Not involved: Chip registries and manufacturing records.

Inputs and outputs

Not involved: Chip registries and manufacturing records.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Training data

Not involved: Hardware-attested weight binding and Chip registries and manufacturing records.

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

Chip registries and manufacturing records

None on the map

1. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
2. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
3. A primer on secure enclaves, Tinfoil (2026). Original
4. Backend infrastructure, Tinfoil (2026). Original
5. How verification works in Tinfoil, Tinfoil (2026). Original
6. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
7. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
8. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
9. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
10. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
11. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
12. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
13. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
14. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
15. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
16. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
17. Covert AI Projects, B. Halstead & T. Larsen (2026). Original