Proposal Explorer

Add claims to see which ones the mechanisms address.

In production

• R3 Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Deterministic and bit-exact inference

No new hardware needed

Deterministic and bit-exact inference

Not counted

Excluded by your filters: Chip registries and manufacturing records and Bounding unexplained information in outputs

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Chip registries and manufacturing records: Analysis · excluded by filters
• Bounding unexplained information in outputs: Independent red-team · excluded by filters
• Deterministic and bit-exact inference: Analysis

Excluded by your filters

• Chip registries and manufacturing records Readiness R1 is below the minimum of R3.
• Bounding unexplained information in outputs Readiness R2 is below the minimum of R3.

Open significant flaws

8 flaws in 3 mechanisms

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{3 5}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this flaw is mitigated. Add

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ²

  Theoretical argument · Significant · Open. On the record

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ³

  Theoretical argument · Significant · Open. On the record

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{7 8}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{6 9}

  Theoretical argument · Significant · Open. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{7 10}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this flaw is mitigated. Add

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ⁶

  Open question · Significant · Open. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{11 13}

  Open question · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹¹

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 Sampled inference recomputation Add
  • Bounding unexplained information in outputs depends on it.
• R1 Remote detection of data centres Add

  Excluded by filters: readiness R1

  • Bears on the open significant flaw “Records cover only chips that were recorded” in Chip registries and manufacturing records. Looks for large data centres that were never declared, which a registry cannot show.
• R1 Side-channel suppression for isolated facilities Add

  Excluded by filters: readiness R1

  • Bears on the open significant flaw “Channels other than checked outputs are outside the bound” in Bounding unexplained information in outputs. Physical side channels need separate suppression, which is this mechanism's purpose.
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
• R2 Bandwidth limits and compartmentalization Add

  Excluded by filters: readiness R2

  • Bounding unexplained information in outputs waits on it. The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound.
• R1 Network taps and certifiers Add

  Excluded by filters: readiness R1

  • Bounding unexplained information in outputs depends on it.

Missing prerequisites

• R3 Sampled inference recomputation needed by Bounding unexplained information in outputs Add
• R2 Bandwidth limits and compartmentalization needed by Bounding unexplained information in outputs Add
• R1 Side-channel suppression for isolated facilities needed by Bounding unexplained information in outputs Add
• R1 Network taps and certifiers needed by Bounding unexplained information in outputs Add

Blockers

12 blockers recorded

• Chip registries and manufacturing records
  • No AI chip registry operates, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{1 2}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{1 2 3}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{3 5}
• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ⁶
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{7 10}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{8 10}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ⁶
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ⁶
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{12 14}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{11 15 21}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ²²
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{10 11}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Not involved: Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Not involved: Chip registries and manufacturing records.

Training data

Not involved: Chip registries and manufacturing records, Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Chip registries and manufacturing records

None on the map

Bounding unexplained information in outputs

None on the map

Deterministic and bit-exact inference

• R2 Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• R3 Verde and RepOps (Gensyn) Product, Gensyn
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
2. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
3. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
4. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
5. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
6. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
7. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
8. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
9. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
10. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
11. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
12. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
13. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
14. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
15. Batch Invariance (vLLM documentation), vLLM project (2026). Original
16. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
17. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
18. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
19. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
20. What is Delphi? (Delphi documentation), Gensyn (2026). Original
21. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
22. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original