Proposal Explorer

Add claims to see which ones the mechanisms address.

Built for an adversarial prover

Bandwidth limits and compartmentalization, Whole-workload recomputation (reproducible packets) and Hardware-enabled guarantees (flexHEG) and guarantee processors

No new hardware needed

Safeguard attestation

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Safeguard attestation: Analysis
• Bandwidth limits and compartmentalization: Analysis
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis

Open significant flaws

18 flaws in 4 mechanisms

• Attestation shows a safeguard ran, not that it is effective in Safeguard attestation

  Proof of guardrail ensures that the guardrail executed, but the guardrail can still err or be jailbroken. Because the guardrail must be open source, a malicious developer can attack it with jailbreaks while still presenting a valid proof. In the authors' evaluation, Llama Guard 3 reached an F1 score of 0.56 on the unsafe class of the ToxicChat dataset. The authors state that proof of guardrail should not be interpreted or advertised as proof of safety. ¹

  Theoretical argument · Significant · Open. On the record

• Selective attestation leaves traffic uncovered in Safeguard attestation

  Attestations are issued per response. In the prototype, the agent offers them when it receives high-stakes questions, so nothing shows that unattested traffic went through the same path. PAL*M's authors note that a prover could cherry-pick favourable executions, and suggest verifier-published nonces or requesting only session-level proofs. A governance analysis notes that auditors also need assurance that all activity is accounted for, since a host could start a second confidential virtual machine that bypasses monitoring. ^{1 4 9}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 On-chip telemetry from timing, memory and performance counters: On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard. A pointer, not evidence that this flaw is mitigated. Add

• Measurements may omit behaviour-relevant configuration or runtime changes in Safeguard attestation

  Every component that influences inference behaviour must be covered by the launch measurement, including feature flags, environment variables and invocation arguments. A launch measurement also does not show that a program keeps running as measured if the kernel is later compromised. ⁹

  Theoretical argument · Significant · Open. On the record

• Components outside the attested boundary in Safeguard attestation

  In the proof-of-guardrail experiments, the guardrail model and the agent's backend model were both reached through external APIs, and the authors leave the decision to trust those APIs to the verifier. The measured wrapper must also have no vulnerability that lets the unmeasured agent bypass the guardrail, for example by executing arbitrary commands inside the enclave. The code's README states that the enclave does not currently restrict the agent's arbitrary command execution, which could be used to bypass guardrails. ^{1 2}

  Theoretical argument · Significant · Open. On the record

• Memory-bus interposition extracts attestation keys and forges attestations in Safeguard attestation

  Applies to variants using the affected Intel or AMD trust roots. PAL*M excludes physical attacks. A TDX-backed safeguard claim against a physical host attacker would be defeated, but these studies do not demonstrate a break of the AWS Nitro proof-of-guardrail prototype or of verifier-side recomputation.

  The TEE findings cover DDR5 attacks on Intel TDX, the H100 relay demonstration, DDR4 attacks on AMD SEV-SNP, and software-only SEV-SNP forgery before AMD's fixes. These are inherited hardware limits; a governance analysis explains why physical access matters in a treaty setting. ^{1 4 7 8 9 10 11 12 13}

  Response: Intel and AMD place the physical attack class outside their threat models, according to the researchers. AMD reports firmware fixes for RMPocalypse.

  Demonstrated attack · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{15 18 19}

  Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ¹⁵

  Theoretical argument · Significant · Open. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ¹⁵

  Theoretical argument · Significant · Open. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ¹⁵

  Open question · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹⁷

  Theoretical argument · Significant · Open. On the record

• Spare compute is outside the scheme in Whole-workload recomputation (reproducible packets)

  The plan states that it does not verify that spare compute is not used for unapproved workloads, because this seems very challenging. Recomputation checks the correctness of declared work, not its completeness. ^{14 20}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Proofs of useful work for capacity accounting: Proposed as one input to accounting for spare capacity on declared hardware. A pointer, not evidence that this flaw is mitigated. Add

• Non-compliant work could be encoded inside compliant-looking packets in Whole-workload recomputation (reproducible packets)

  The plan notes that an AI company might try to encode a non-compliant workload inside a workload that looks compliant on the surface. ¹⁴

  Theoretical argument · Significant · Open. On the record

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{26 28}

  Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ²⁶

  Theoretical argument · Significant · Open. On the record

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{25 27}

  Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ²⁶

  Theoretical argument · Significant · Open. On the record

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{26 27}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this flaw is mitigated. Add

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{25 27}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R1 Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this flaw is mitigated. Add

Not yet demonstrated

R1 Whole-workload recomputation (reproducible packets) and R1 Hardware-enabled guarantees (flexHEG) and guarantee processors

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R2 On-chip telemetry from timing, memory and performance counters Add
  • Bears on the open significant flaw “Selective attestation leaves traffic uncovered” in Safeguard attestation. On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard.
• R1 Chip registries and manufacturing records Add
  • Bears on the open significant flaw “Supply-chain diversion and hidden backdoors” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
• R1 Proofs of useful work for capacity accounting Add
  • Bears on the open significant flaw “Spare compute is outside the scheme” in Whole-workload recomputation (reproducible packets). Proposed as one input to accounting for spare capacity on declared hardware.
• R1 Remote detection of data centres Add
  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
• R3 Deterministic and bit-exact inference Add
  • Whole-workload recomputation (reproducible packets) waits on it. Workloads are not reproducible by default, and achieving reproducibility may cost performance.
• R3 Model identity attestation Add
  • Safeguard attestation waits on it. Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation.
• R3 TEE remote attestation for AI workloads Add
  • Safeguard attestation waits on it. Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference.
  • Safeguard attestation waits on it. Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
• R2 Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
• R1 Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
  • Whole-workload recomputation (reproducible packets) waits on it. All traffic must reach the recomputation server via network taps, and the server's integrity is critical.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Safeguard attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors Add
• R3 Model identity attestation needed by Safeguard attestation Add
• R2 Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add
• R3 Deterministic and bit-exact inference needed by Whole-workload recomputation (reproducible packets) Add
• R1 Network taps and certifiers needed by Whole-workload recomputation (reproducible packets) Add
• R1 Chip registries and manufacturing records needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Safeguard attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors
• Tamper evidence for verifier devices relied on by Bandwidth limits and compartmentalization and Hardware-enabled guarantees (flexHEG) and guarantee processors
• Network taps and certifiers relied on by Bandwidth limits and compartmentalization and Whole-workload recomputation (reproducible packets)

Blockers

18 blockers recorded

• Safeguard attestation
  • No published design shows that all of a provider's traffic passes through the attested safeguard path; current evidence covers individual attested responses. Coverage & hidden compute ^{1 9}
  • Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference. Performance & compatibility. Waits on TEE remote attestation for AI workloads ^{9 31}
  • Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack. Hardware trust. Waits on TEE remote attestation for AI workloads ^{7 9}
  • Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation. Evidence binding. Waits on Model identity attestation ^{31 32}
  • No independent red-team or audit of a safeguard-attestation system has been published, and the available prototypes are described by their authors as proofs of concept that have not been stress-tested by a counterparty. Adversarial validation ^{2 6}
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ¹⁵
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ¹³
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{15 17}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{15 18 19}
• Whole-workload recomputation (reproducible packets)
  • Workloads are not reproducible by default, and achieving reproducibility may cost performance. Performance & compatibility. Waits on Deterministic and bit-exact inference ¹⁴
  • Network packets are not individually reproducible by default; making them so may need considerable software, firmware and hardware work. Amodo rates this 'not on track'. Performance & compatibility ²²
  • All traffic must reach the recomputation server via network taps, and the server's integrity is critical. Hardware trust. Waits on Network taps and certifiers ^{14 22}
  • Recomputing training steps needs checkpoints: writing one at every step would cost more than 100% overhead, so Amodo's design needs a spare data-parallel replica that tracks the weights instead. Performance & compatibility ²⁰
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ²⁶
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{26 28}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{25 27}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ²⁵
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ²⁷

From the family or selected implementation's record. ?

Model weights

Depends on the design for Safeguard attestation and Whole-workload recomputation (reproducible packets).

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Bandwidth limits and compartmentalization.

Inputs and outputs

Depends on the design for Safeguard attestation and Whole-workload recomputation (reproducible packets).

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Bandwidth limits and compartmentalization.

Training data

Depends on the design for Whole-workload recomputation (reproducible packets).

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Safeguard attestation and Bandwidth limits and compartmentalization.

Safeguard attestation

None on the map

Bandwidth limits and compartmentalization

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Whole-workload recomputation (reproducible packets)

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

1. Proof-of-Guardrail in AI Agents and What (Not) to Trust from It, X. Jin et al. (2026). Original
2. Verifiable-ClawGuard: proof-of-guardrail reference code, SaharaLabsAI (2026). Original
3. Safety Without Compromising on Privacy, D. McCann-Sayles et al. (2026). Original
4. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
5. Enabling Verifiably-Scoped Monitoring through Large Language Models and Trusted Compute, B. Penchas et al. (2026). Original
6. Auditor-in-a-Box: Tools for Third-Party Auditing, R. Rinberg & B. Penchas (2026). Original
7. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
8. DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes, J. De Meulemeester et al. (2026). Original
9. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
10. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
11. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
12. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
13. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
14. Verification Plan, R. Dean (2026). Original
15. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
16. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
17. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
18. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
19. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
20. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
21. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
22. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
23. Get Involved in Verification, AI Futures Project (2026). Original
24. Proof-of-Learning is Currently More Broken Than You Think, C. Fang et al. (2023). Original
25. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
26. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
27. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
28. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
29. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
30. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original
31. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
32. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original