Proposal Explorer

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Built for an adversarial prover

Bounding unexplained information in outputs and Bandwidth limits and compartmentalization

No new hardware needed

On-chip telemetry from timing, memory and performance counters

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Bounding unexplained information in outputs: Independent red-team
• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Bandwidth limits and compartmentalization: Analysis

Open significant failures

5 failures in 3 mechanisms

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{2 3}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this failure is mitigated. Add

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ⁸

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{9 10}

  Known failure · Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ¹²

  Known failure · Theoretical argument · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹⁴

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{1 4}

  Scope limitation · Theoretical argument. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{2 5}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this failure is mitigated. Add

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{6 8}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁶

  Scope limitation · Theoretical argument. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ¹²

  Scope limitation · Theoretical argument. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ¹²

  Scope limitation · Open question. On the record

Open questions

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ¹

  Open question · Open question. On the record

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁶

  Open question · Open question. On the record

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{12 15 16}

  Open question · Theoretical argument. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Prompt-controlled entropy inflation widens the covert channel” in Bounding unexplained information in outputs. Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.
  • Bounding unexplained information in outputs waits on it. Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata.
• Research demo Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• Proposed Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
  • Bounding unexplained information in outputs depends on it.
• Proposed Side-channel suppression for isolated facilities Add
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
• Operational use Sampled inference recomputation Add
  • Bounding unexplained information in outputs depends on it.
• Operational use TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: needs new chips

  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.

Missing prerequisites

• Operational use Sampled inference recomputation needed by Bounding unexplained information in outputs Add
• Proposed Side-channel suppression for isolated facilities needed by Bounding unexplained information in outputs Add
• Proposed Network taps and certifiers needed by Bounding unexplained information in outputs Add
• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add
• Research demo Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Shared foundations

• Network taps and certifiers relied on by Bounding unexplained information in outputs and Bandwidth limits and compartmentalization

Blockers

13 blockers recorded

• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{2 5}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{3 5}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ¹
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ¹
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{7 8}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{9 10}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁶
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ⁸
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ¹²
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ⁵
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{12 14}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{12 15 16}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Bounding unexplained information in outputs and On-chip telemetry from timing, memory and performance counters.

Not involved: Bandwidth limits and compartmentalization.

Inputs and outputs

Depends on the design for Bounding unexplained information in outputs and On-chip telemetry from timing, memory and performance counters.

Not involved: Bandwidth limits and compartmentalization.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Bounding unexplained information in outputs and Bandwidth limits and compartmentalization.

Bounding unexplained information in outputs

None on the map

On-chip telemetry from timing, memory and performance counters

None on the map

Bandwidth limits and compartmentalization

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

1. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
2. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
3. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
4. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
5. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
6. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
7. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
8. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
9. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
10. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
11. Verification Plan, R. Dean (2026). Original
12. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
13. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
14. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
15. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
16. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original