Proposal Explorer
ResetA verification proposal from the AI Verification Tech Map, from its records of 2026-10-09. https://trustbutveri.fyi/explorer/?mechanisms=M-0014,M-0003,M-0019&chips=existing&cols=hardware
Analysis
Applied filters: Chips: Existing chips only. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Minimum development status, Attack testing, Keep hidden from the verifier.
Overview
| Mechanism | Development | Security evidence | Open failures | Hardware |
|---|---|---|---|---|
| Bandwidth limits and compartmentalization | Research demo | Published security analysis | 2 significant | Retrofit device |
| Whole-workload recomputation (reproducible packets) | Proposed | No published adversarial analysis recorded | none | Retrofit device |
| Chip registries and manufacturing records | Proposed | Published security analysis | 1 significant | Existing features |
- Open failures: n critical n significant n minor
Claim coverageNo claims yet
Add claims to see which ones the mechanisms address.
Properties2 built for an adversarial prover
- Built for an adversarial prover
- Bandwidth limits and compartmentalization and Whole-workload recomputation (reproducible packets)
- No new hardware needed
- Chip registries and manufacturing records
Attack testing2 mechanisms with published testing
Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.
Limits5 scope limitations · 2 open questions · 2 not yet demonstrated · 2 mechanisms with open significant failures
- Open significant failures
3 failures in 2 mechanisms
Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization
Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. 2
Known failure · Theoretical argument · Significant · Open. On the record
Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization
In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. 5
Known failure · Theoretical argument · Significant · Open. On the record
Documents and serial numbers can be forged in Chip registries and manufacturing records
Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. 14
Known failure · Theoretical argument · Significant · Open. On the record
- Scope limitations
Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization
More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. 2
Scope limitation · Theoretical argument. On the record
Training within one pod is not covered in Bandwidth limits and compartmentalization
Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. 2
Scope limitation · Open question. On the record
Spare compute is outside the scheme in Whole-workload recomputation (reproducible packets)
The plan states that it does not verify that spare compute is not used for unapproved workloads, because this seems very challenging. Recomputation checks the correctness of declared work, not its completeness. 1 8
Scope limitation · Theoretical argument. On the record
Related mechanism Proposed Proofs of useful work for capacity accounting: Proposed as one input to accounting for spare capacity on declared hardware. A pointer, not evidence that this failure is mitigated. Add
Records cover only chips that were recorded in Chip registries and manufacturing records
A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. 15 17
Scope limitation · Theoretical argument. On the record
Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add
Insiders could alter records before they are fixed in Chip registries and manufacturing records
Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. 15
Scope limitation · Theoretical argument. On the record
- Open questions
Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization
DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. 2 6 7
Open question · Theoretical argument. On the record
Non-compliant work could be encoded inside compliant-looking packets in Whole-workload recomputation (reproducible packets)
The plan notes that an AI company might try to encode a non-compliant workload inside a workload that looks compliant on the surface. 1
Open question · Theoretical argument. On the record
- Not yet demonstrated
- Proposed Whole-workload recomputation (reproducible packets) and Proposed Chip registries and manufacturing records
Possible additions3 for dependencies
Mechanisms on the map that are not in the proposal. Pointers, not recommendations.
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- Whole-workload recomputation (reproducible packets) waits on it. Workloads are not reproducible by default, and achieving reproducibility may cost performance.
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- Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
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- Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
- Whole-workload recomputation (reproducible packets) waits on it. All traffic must reach the recomputation server via network taps, and the server's integrity is critical.
Dependencies3 missing prerequisites · 1 shared foundation · 11 blockers
- Missing prerequisites
- Research demo Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add
- Operational use Deterministic and bit-exact inference needed by Whole-workload recomputation (reproducible packets) Add
- Proposed Network taps and certifiers needed by Whole-workload recomputation (reproducible packets) Add
- Shared foundations
- Network taps and certifiers relied on by Bandwidth limits and compartmentalization and Whole-workload recomputation (reproducible packets)
- Blockers
11 blockers recorded
- Bandwidth limits and compartmentalization
- No cap that a verifier can check has been implemented or red-teamed. Adversarial validation 2
- The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers 3
- Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices 2 5
- Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds 2 6 7
- Whole-workload recomputation (reproducible packets)
- Workloads are not reproducible by default, and achieving reproducibility may cost performance. Performance & compatibility. Waits on Deterministic and bit-exact inference 1
- Network packets are not individually reproducible by default; making them so may need considerable software, firmware and hardware work. Amodo rates this 'not on track'. Performance & compatibility 10
- All traffic must reach the recomputation server via network taps, and the server's integrity is critical. Hardware trust. Waits on Network taps and certifiers 1 10
- Recomputing training steps needs checkpoints: writing one at every step would cost more than 100% overhead, so Amodo's design needs a spare data-parallel replica that tracks the weights instead. Performance & compatibility 8
- Chip registries and manufacturing records
- No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance 13 14
- Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust 13 14 15
- Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute 15 17
- Bandwidth limits and compartmentalization
What the verifier sees1 depend on design
From the family or selected implementation's record.
- Model weights
Depends on the design for Whole-workload recomputation (reproducible packets).
Not involved: Bandwidth limits and compartmentalization and Chip registries and manufacturing records.
- Inputs and outputs
Depends on the design for Whole-workload recomputation (reproducible packets).
Not involved: Bandwidth limits and compartmentalization and Chip registries and manufacturing records.
- Training data
Depends on the design for Whole-workload recomputation (reproducible packets).
Not involved: Bandwidth limits and compartmentalization and Chip registries and manufacturing records.
Exposure notes
- Bandwidth limits and compartmentalization: Caps traffic between groups of chips; it does not read the traffic's content.
- Whole-workload recomputation (reproducible packets): Recomputing sampled units needs weights and sampled inputs or training data inside the checking environment. The design depends on securing that environment; disclosure depends on its confidentiality boundary. 1 8
- Chip registries and manufacturing records: Records chip identities and owners; it does not handle model data.
Implementations2 systems
- Bandwidth limits and compartmentalization
- Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
- Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND
- Whole-workload recomputation (reproducible packets)
- Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
- Chip registries and manufacturing records
- None on the map
Sources17 cited
- Verification Plan, R. Dean (2026). Original
- Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
- A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
- De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
- The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
- DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
- Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
- Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
- Scaling Recomputation Inference Verification, Amodo Design (2026). Original
- AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
- Get Involved in Verification, AI Futures Project (2026). Original
- Proof-of-Learning is Currently More Broken Than You Think, C. Fang et al. (2023). Original
- Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
- Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
- TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
- Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
- Covert AI Projects, B. Halstead & T. Larsen (2026). Original
Share the link to this proposal. This proposal is also available as plain text and JSON.
Filter mechanisms
Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.
23 of 25 mechanisms match · Clear all
Prover
How far can the party being checked be trusted?
The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.
Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions
Verifier devices on site
May the verifier install its own hardware at the prover's sites?
Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.
"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions
Prover cooperation
How much must the prover take part?
Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.
"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions
Chips
May the proposal depend on new chip designs?
New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.
"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions
Minimum development status
Development status
A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.
Keeps mechanisms whose readiness level is at least this one. Definitions
Attack testing
How hard has each mechanism been attacked in public?
The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.
Keeps mechanisms whose strongest published attack testing is at least this. Definitions
Keep hidden from the verifier
What must the verifier never see? Choose any.
Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.
Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.
Claims
A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.
- Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
- Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
- Unaddressed. No mechanism in the proposal addresses this claim.
Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, development status, security evidence, assumptions and findings.
Mechanisms
A mechanism is a general technique for verifying claims. Its badge is its development status for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.
- Aimed at the claim: verifying it is a direct purpose of the mechanism.
- Supports the claim: helps verify it without being aimed at it.
- Faint: excluded by your filters, so it does not count towards claim coverage.
Overview
One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Failure counts are per mechanism. Summary counts name mechanisms with open failures, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.
What the verifier sees
For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.
Possible additions
Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. They are pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure. Links from failures are the editors' reading of the two records.
Start from a goal
A goal is something a rule or agreement about AI sets out to achieve. Choosing one loads the claims it needs verified. Your mechanisms and filters stay as they are.
- Cap frontier training2 direct, 3 supportingKeep every AI training run below an agreed amount of compute.
- Pause frontier AI development2 direct, 3 supportingStop new AI training runs and experiments for an agreed period, while existing models stay in service.
- Deploy only evaluated models2 direct, 3 supportingDeploy powerful AI models widely only after their risks have been evaluated and judged manageable.
- Prevent catastrophic misuse2 direct, 2 supportingKeep capable AI models from helping anyone carry out catastrophic attacks, such as biological or chemical ones.
- Prevent weight theft1 direct, 1 supportingKeep the weights of capable AI models from being copied out of the facilities that hold them.
- Enforce chip export controls1 directKeep export-controlled AI chips at the destinations they were authorised for.
Start from a published design
Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.
- AI 2040 inference-only verification stack7 mechanismsProposed architecture, AI Futures Project
- Low-trust AI compute verification system overview7 mechanismsProposed architecture, Machine Intelligence Research Institute
- RAND secure inference data center (SIDC) design2 mechanismsProposed architecture, RAND