Proposal Explorer

Add claims to see which ones the mechanisms address.

Built for an adversarial prover

Whole-workload recomputation (reproducible packets) and Network taps and certifiers

No new hardware needed

Chip registries and manufacturing records

Failures since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ¹²

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip registries and manufacturing records: Analysis
• Network taps and certifiers: Analysis

Open significant failures

3 failures in 2 mechanisms

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ⁸

  Known failure · Theoretical argument · Significant · Open. On the record

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{12 19}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Research demo Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this failure is mitigated. Add

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ¹⁵

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Spare compute is outside the scheme in Whole-workload recomputation (reproducible packets)

  The plan states that it does not verify that spare compute is not used for unapproved workloads, because this seems very challenging. Recomputation checks the correctness of declared work, not its completeness. ^{1 2}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Proofs of useful work for capacity accounting: Proposed as one input to accounting for spare capacity on declared hardware. A pointer, not evidence that this failure is mitigated. Add

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{9 11}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ⁹

  Scope limitation · Theoretical argument. On the record

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{13 20}

  Scope limitation · Open question. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ¹³

  Scope limitation · Open question. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ¹²

  Scope limitation · Open question. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this failure is mitigated. Add

Open questions

• Non-compliant work could be encoded inside compliant-looking packets in Whole-workload recomputation (reproducible packets)

  The plan notes that an AI company might try to encode a non-compliant workload inside a workload that looks compliant on the surface. ¹

  Open question · Theoretical argument. On the record

Not yet demonstrated

Proposed Whole-workload recomputation (reproducible packets), Proposed Chip registries and manufacturing records and Proposed Network taps and certifiers

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  • Whole-workload recomputation (reproducible packets) waits on it. Workloads are not reproducible by default, and achieving reproducibility may cost performance.
  • Network taps and certifiers waits on it. Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
• Research demo Bounding unexplained information in outputs Add
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
• Research demo Tamper evidence for verifier devices Add
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• Proposed Side-channel suppression for isolated facilities Add
  • Network taps and certifiers waits on it. Radio, power-line and thermal channels are not addressed by network-level designs.
• Operational use Sampled inference recomputation Add
  • Network taps and certifiers depends on it.

Missing prerequisites

• Operational use Deterministic and bit-exact inference needed by Whole-workload recomputation (reproducible packets) and Network taps and certifiers Add
• Operational use Sampled inference recomputation needed by Network taps and certifiers Add
• Research demo Tamper evidence for verifier devices needed by Network taps and certifiers Add
• Proposed Side-channel suppression for isolated facilities needed by Network taps and certifiers Add

Shared foundations

• Deterministic and bit-exact inference relied on by Whole-workload recomputation (reproducible packets) and Network taps and certifiers

Blockers

12 blockers recorded

• Whole-workload recomputation (reproducible packets)
  • Workloads are not reproducible by default, and achieving reproducibility may cost performance. Performance & compatibility. Waits on Deterministic and bit-exact inference ¹
  • Network packets are not individually reproducible by default; making them so may need considerable software, firmware and hardware work. Amodo rates this 'not on track'. Performance & compatibility ⁴
  • All traffic must reach the recomputation server via network taps, and the server's integrity is critical. Hardware trust. Waits on Network taps and certifiers ^{1 4}
  • Recomputing training steps needs checkpoints: writing one at every step would cost more than 100% overhead, so Amodo's design needs a spare data-parallel replica that tracks the weights instead. Performance & compatibility ²
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{7 8}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{7 8 9}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{9 11}
• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{20 21}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ¹²
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{12 14}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹²
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ¹²

From the family or selected implementation's record. ?

Model weights

Depends on the design for Whole-workload recomputation (reproducible packets) and Network taps and certifiers.

Not involved: Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for Whole-workload recomputation (reproducible packets) and Network taps and certifiers.

Not involved: Chip registries and manufacturing records.

Training data

Depends on the design for Whole-workload recomputation (reproducible packets) and Network taps and certifiers.

Not involved: Chip registries and manufacturing records.

Whole-workload recomputation (reproducible packets)

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

Chip registries and manufacturing records

None on the map

Network taps and certifiers

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

1. Verification Plan, R. Dean (2026). Original
2. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
3. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
4. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
5. Get Involved in Verification, AI Futures Project (2026). Original
6. Proof-of-Learning is Currently More Broken Than You Think, C. Fang et al. (2023). Original
7. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
8. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
9. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
10. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
11. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
12. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
13. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
14. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
15. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
16. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
17. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
18. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
19. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
20. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
21. Network Traffic Hashing, Amodo Design (2026). Original