Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Sampled inference recomputation for checking untrusted workers' activations against the declared model, prompt and precision

Built for an adversarial prover

Sampled inference recomputation

No new hardware needed

Sampled inference recomputation and Chip registries and manufacturing records

Not counted

Excluded by your filters: Hardware-enabled guarantees (flexHEG) and guarantee processors

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Sampled inference recomputation: Analysis
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis · excluded by filters
• Chip registries and manufacturing records: Analysis

Excluded by your filters

• Hardware-enabled guarantees (flexHEG) and guarantee processors Needs changes to future chip designs; the filter allows existing chips only.

Open significant failures

6 failures in 3 mechanisms

• Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

  Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. ^{1 9 12}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this failure is mitigated. Add

• Some inference optimizations are not covered in Sampled inference recomputation

  TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. ^{2 3}

  Known failure · Theoretical argument · Significant · Open. On the record

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{16 18}

  Known failure · Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ¹⁶

  Known failure · Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ¹⁶

  Known failure · Theoretical argument · Significant · Open. On the record

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ²²

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Only recorded traffic is checked in Sampled inference recomputation

  Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. ^{1 13}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this failure is mitigated. Add

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{15 17}

  Scope limitation · Theoretical argument. On the record

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{15 17}

  Scope limitation · Open question. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this failure is mitigated. In the proposal.

  Related mechanism Proposed Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this failure is mitigated. Add

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{23 25}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ²³

  Scope limitation · Theoretical argument. On the record

Open questions

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{16 17}

  Open question · Open question. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this failure is mitigated. In the proposal.

Open minor failures

1 mechanism with minor failures

• Mixed hardware widens the honest baseline in Sampled inference recomputation

  When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. ²

  Known failure · Open question · Minor · Open. On the record

Not yet demonstrated

Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors and Proposed Chip registries and manufacturing records

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Tolerance for numerical noise leaves a covert channel” in Sampled inference recomputation. Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration.
• Research demo Tamper evidence for verifier devices Add
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
• Proposed Network taps and certifiers Add
  • Sampled inference recomputation waits on it. In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface.
• Operational use TEE remote attestation for AI workloads Add
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add

Blockers

13 blockers recorded

• Sampled inference recomputation
  • In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface. Coverage & hidden compute. Waits on Network taps and certifiers ^{8 26}
  • In retrofit designs, the recomputation server must sit inside the prover's data centre, possibly under the prover's physical control, and still be protected from a compromised provider, which Amodo rates 'not on track'. Hardware trust ^{1 8}
  • No independent red-team of a recomputation consistency check has been published (the one independent attack study targets the weight-exfiltration bound), and Amodo rates recomputation red-teaming 'not started'. Adversarial validation ^{8 9}
  • Tolerance-based checks need calibration on trusted hardware and exact knowledge of the provider's sampling procedure, and in one prototype a sampling-implementation mismatch produced large spurious differences. Performance & compatibility ^{2 7}
  • The verifier needs the model weights, so checking a closed-weights model requires a trusted, confidential recomputation environment, which the retrofit designs place inside the prover's facility. Privacy & leakage ^{2 13 14}
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ¹⁶
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{16 18}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{15 17}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ¹⁵
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ¹⁷
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{21 22}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{21 22 23}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{23 25}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Sampled inference recomputation.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for Sampled inference recomputation.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Chip registries and manufacturing records.

Training data

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Sampled inference recomputation and Chip registries and manufacturing records.

Sampled inference recomputation

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Research demo DiFR (Divergence From Reference) Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)
• Operational use TOPLOC Open-source project, Prime Intellect

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

Chip registries and manufacturing records

None on the map

1. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
2. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original
3. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
4. PrimeIntellect-ai/toploc (GitHub repository), Prime Intellect (2025). Original
5. INTELLECT-2: A Reasoning Model Trained Through Globally Decentralized Reinforcement Learning, Prime Intellect Team et al. (2025). Original
6. adamkarvonen/difr (GitHub repository), A. Karvonen (2025). Original
7. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
8. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
9. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
10. SYNTHETIC-2 Release: Four Million Collaboratively Generated Reasoning Traces, Prime Intellect (2025). Original
11. An Inference Verification Prototype — Stage 1, Amodo Design (2026). Original
12. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
13. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
14. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
15. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
16. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
17. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
18. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
19. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
20. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original
21. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
22. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
23. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
24. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
25. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
26. Verification Plan, R. Dean (2026). Original