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Bandwidth limits and compartmentalization and Tamper evidence for verifier devices

No new hardware needed

Chip registries and manufacturing records

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Bandwidth limits and compartmentalization: Analysis
• Tamper evidence for verifier devices: Analysis
• Chip registries and manufacturing records: Analysis

Open significant failures

5 failures in 3 mechanisms

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ²

  Known failure · Theoretical argument · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ⁵

  Known failure · Theoretical argument · Significant · Open. On the record

• Seals are often defeated with simple methods in Tamper evidence for verifier devices

  Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor.

  In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones. ^{14 15}

  Known failure · Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

• Attack classes outside published models in Tamper evidence for verifier devices

  The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure.

  The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure. ^{8 9 16}

  Known failure · Open question · Significant · Open · Mechanism-class evidence. On the record

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ¹⁸

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ²

  Scope limitation · Theoretical argument. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ²

  Scope limitation · Open question. On the record

• Security depends on inspection protocols in Tamper evidence for verifier devices

  An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier.

  Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated. ^{13 15}

  Scope limitation · Theoretical argument · Mechanism-class evidence. On the record

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{19 21}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ¹⁹

  Scope limitation · Theoretical argument. On the record

Open questions

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{2 6 7}

  Open question · Theoretical argument. On the record

Not yet demonstrated

Proposed Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.

Blockers

11 blockers recorded

• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ²
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ³
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{2 5}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{2 6 7}
• Tamper evidence for verifier devices
  • No tamper-evident enclosure has been designed for AI verifier hardware at retrofit scale. Hardware trust ³
  • Battery-backed designs add bulk, limit operating temperature (+10 °C to +35 °C for the IBM 4765) and complicate transport. Performance & compatibility ⁹
  • Active monitoring needs power, and visual inspection of large enclosures faces access limits. Access & governance ¹³
  • No evaluation has been published in the AI verification setting. Adversarial validation ³
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{17 18}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{17 18 19}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{19 21}

From the family or selected implementation's record. ?

Model weights

Not involved: Bandwidth limits and compartmentalization, Tamper evidence for verifier devices and Chip registries and manufacturing records.

Inputs and outputs

Not involved: Bandwidth limits and compartmentalization, Tamper evidence for verifier devices and Chip registries and manufacturing records.

Training data

Not involved: Bandwidth limits and compartmentalization, Tamper evidence for verifier devices and Chip registries and manufacturing records.

Bandwidth limits and compartmentalization

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

Tamper evidence for verifier devices

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

Chip registries and manufacturing records

None on the map

1. Verification Plan, R. Dean (2026). Original
2. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
3. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
4. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
5. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
6. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
7. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
8. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). Original
9. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). Original
10. ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection, T. Mosavirik et al. (2023). Original
11. IBM 4765 Cryptographic Coprocessor Security Module: Security Policy, IBM Corporation (2012). Original
12. PHYSEC SEAL: Change detection for maximum safety, PHYSEC GmbH (2026). Original
13. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). Original
14. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). Original
15. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). Original
16. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). Original
17. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
18. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
19. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
20. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
21. Covert AI Projects, B. Halstead & T. Larsen (2026). Original