Proposal Explorer

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Built for an adversarial prover

Bounding unexplained information in outputs and Network taps and certifiers

Failures since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ¹²

Not counted

Excluded by your filters: Hardware-enabled guarantees (flexHEG) and guarantee processors

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Bounding unexplained information in outputs: Independent red-team
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis · excluded by filters
• Network taps and certifiers: Analysis

Excluded by your filters

• Hardware-enabled guarantees (flexHEG) and guarantee processors Needs changes to future chip designs; the filter allows existing chips only.

Open significant failures

6 failures in 3 mechanisms

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{2 3}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this failure is mitigated. Add

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{7 9}

  Known failure · Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ⁷

  Known failure · Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ⁷

  Known failure · Theoretical argument · Significant · Open. On the record

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{3 12}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Research demo Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this failure is mitigated. In the proposal.

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ¹⁵

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{1 4}

  Scope limitation · Theoretical argument. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{2 5}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this failure is mitigated. Add

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{6 8}

  Scope limitation · Theoretical argument. On the record

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{6 8}

  Scope limitation · Open question. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Proposed Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this failure is mitigated. Add

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{13 19}

  Scope limitation · Open question. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ¹³

  Scope limitation · Open question. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ¹²

  Scope limitation · Open question. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this failure is mitigated. Add

Open questions

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ¹

  Open question · Open question. On the record

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{7 8}

  Open question · Open question. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this failure is mitigated. Add

Not yet demonstrated

Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors and Proposed Network taps and certifiers

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Prompt-controlled entropy inflation widens the covert channel” in Bounding unexplained information in outputs. Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  • Bounding unexplained information in outputs waits on it. Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata.
  • Network taps and certifiers waits on it. Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
• Research demo Bandwidth limits and compartmentalization Add
  • Bounding unexplained information in outputs waits on it. The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound.
• Research demo Tamper evidence for verifier devices Add
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• Proposed Chip registries and manufacturing records Add
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
• Proposed Side-channel suppression for isolated facilities Add
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
  • Network taps and certifiers waits on it. Radio, power-line and thermal channels are not addressed by network-level designs.
• Operational use Sampled inference recomputation Add
  • Bounding unexplained information in outputs depends on it.
  • Network taps and certifiers depends on it.
• Operational use TEE remote attestation for AI workloads Add
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.

Missing prerequisites

• Operational use Sampled inference recomputation needed by Bounding unexplained information in outputs and Network taps and certifiers Add
• Research demo Bandwidth limits and compartmentalization needed by Bounding unexplained information in outputs Add
• Proposed Side-channel suppression for isolated facilities needed by Bounding unexplained information in outputs and Network taps and certifiers Add
• Operational use TEE remote attestation for AI workloads needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add
• Proposed Chip registries and manufacturing records needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add
• Operational use Deterministic and bit-exact inference needed by Network taps and certifiers Add
• Research demo Tamper evidence for verifier devices needed by Network taps and certifiers Add

Shared foundations

• Sampled inference recomputation relied on by Bounding unexplained information in outputs and Network taps and certifiers
• Side-channel suppression for isolated facilities relied on by Bounding unexplained information in outputs and Network taps and certifiers
• Deterministic and bit-exact inference relied on by Bounding unexplained information in outputs and Network taps and certifiers
• Tamper evidence for verifier devices relied on by Hardware-enabled guarantees (flexHEG) and guarantee processors and Network taps and certifiers

Blockers

15 blockers recorded

• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{2 5}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{3 5}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ¹
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ¹
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ⁷
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{7 9}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{6 8}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ⁶
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ⁸
• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{19 20}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ¹²
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{5 12}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹²
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ¹²

From the family or selected implementation's record. ?

Model weights

Depends on the design for Bounding unexplained information in outputs and Network taps and certifiers.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Inputs and outputs

Depends on the design for Bounding unexplained information in outputs and Network taps and certifiers.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Training data

Depends on the design for Network taps and certifiers.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Bounding unexplained information in outputs.

Bounding unexplained information in outputs

None on the map

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

Network taps and certifiers

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

1. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
2. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
3. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
4. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
5. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
6. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
7. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
8. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
9. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
10. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
11. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original
12. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
13. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
14. Verification Plan, R. Dean (2026). Original
15. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
16. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
17. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
18. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
19. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
20. Network Traffic Hashing, Amodo Design (2026). Original