Proposal Explorer

Add claims to see which ones the mechanisms address.

In production

• R3 Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Network taps and certifiers, Side-channel suppression for isolated facilities and Deterministic and bit-exact inference

No new hardware needed

Deterministic and bit-exact inference

Flaws since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ¹

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Network taps and certifiers: Analysis
• Side-channel suppression for isolated facilities: Analysis
• Deterministic and bit-exact inference: Analysis

Open significant flaws

9 flaws in 3 mechanisms

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{1 9}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R3 Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this flaw is mitigated. In the proposal.

  Related mechanism R2 Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this flaw is mitigated. Add

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{2 10}

  Open question · Significant · Open. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ²

  Open question · Significant · Open. On the record

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ⁵

  Theoretical argument · Significant · Open. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ¹

  Open question · Significant · Open. On the record

  Related mechanism R1 Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

  Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ¹¹

  Theoretical argument · Significant · Open. On the record

• Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

  Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ¹¹

  Theoretical argument · Significant · Open. On the record

• Inspection assumptions may not hold in Side-channel suppression for isolated facilities

  The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ¹¹

  Open question · Significant · Open. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{12 14}

  Open question · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹²

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Network taps and certifiers and R1 Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R2 Bounding unexplained information in outputs Add
  • Bears on the open significant flaw “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
• R2 Tamper evidence for verifier devices Add
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• R3 Sampled inference recomputation Add
  • Network taps and certifiers depends on it.

Missing prerequisites

• R3 Sampled inference recomputation needed by Network taps and certifiers Add
• R2 Tamper evidence for verifier devices needed by Network taps and certifiers Add

Blockers

11 blockers recorded

• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{10 22}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ¹
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{1 3}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ¹
• Side-channel suppression for isolated facilities
  • No prototype or red-team exists; the design is a first-pass viability study. Adversarial validation ¹¹
  • Volume costs of TEMPEST-grade power-line filters are uncertain, because existing products are mostly made to order. Performance & compatibility ¹¹
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{13 15}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{12 16 23}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ²⁴
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{3 12}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Network taps and certifiers and Deterministic and bit-exact inference.

Not involved: Side-channel suppression for isolated facilities.

Inputs and outputs

Depends on the design for Network taps and certifiers and Deterministic and bit-exact inference.

Not involved: Side-channel suppression for isolated facilities.

Training data

Depends on the design for Network taps and certifiers.

Not involved: Side-channel suppression for isolated facilities and Deterministic and bit-exact inference.

Network taps and certifiers

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

Side-channel suppression for isolated facilities

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Deterministic and bit-exact inference

• R2 Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• R3 Verde and RepOps (Gensyn) Product, Gensyn
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
2. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
3. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
4. Verification Plan, R. Dean (2026). Original
5. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
6. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
7. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
8. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
9. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
10. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
11. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
12. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
13. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
14. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
15. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
16. Batch Invariance (vLLM documentation), vLLM project (2026). Original
17. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
18. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
19. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
20. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
21. What is Delphi? (Delphi documentation), Gensyn (2026). Original
22. Network Traffic Hashing, Amodo Design (2026). Original
23. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
24. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original