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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0017,M-0013&implementations=M-0017:I-0011&cols=sees

Claims

Mechanisms2

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Analysis

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MechanismReadinessOpen flawsVerifier sees
Tamper evidence for verifier devicesAI 2040 inference-only verification stack R13 significantFamily context belowW unspecifiedI unspecifiedT unspecified
Network taps and certifiers R15 significantW dependsI dependsT depends
  • Open flaws: n critical n significant n minor
  • Verifier sees model weights (W), inputs and outputs (I), training data (T): W shown W depends W hidden W not involved W unspecified
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

Properties2 built for an adversarial prover
Flaws since mitigated
  • Verifier dictionary attacks on hashes in Network taps and certifiers 14
Attack testing1 mechanism with published testing

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

Limits1 family with findings to check · 2 not yet demonstrated · 2 mechanisms with open significant findings
Family findings
  • Tamper evidence for verifier devices

    Context for AI 2040 inference-only verification stack. These findings concern the family or other implementations; applicability must be checked against their stated scope.

    • Seals are often defeated with simple methods in Tamper evidence for verifier devices

      Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor.

      In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones. 8 9

      Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

    • Security depends on inspection protocols in Tamper evidence for verifier devices

      An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier.

      Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated. 9 10

      Theoretical argument · Significant · Open · Mechanism-class evidence. On the record

    • Attack classes outside published models in Tamper evidence for verifier devices

      The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure.

      The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure. 11 12 13

      Open question · Significant · Open · Mechanism-class evidence. On the record

Open significant flaws
8 flaws in 2 mechanisms
  • The recomputation server must be trusted in AI 2040 inference-only verification stack

    The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track. 1 2 4

    Theoretical argument · Significant · Open. On the record

  • Spare compute is not verified in AI 2040 inference-only verification stack

    The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs. 1

    Theoretical argument · Significant · Open. On the record

  • A recomputation family degrades against prompt-controlling adversaries in AI 2040 inference-only verification stack

    The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving. 1 2 6 7

    Demonstrated attack · Significant · Open. On the record

  • Output nondeterminism leaves covert capacity in Network taps and certifiers

    Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. 7 14

    Theoretical argument · Significant · Open. On the record

    Related mechanism R3 Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this flaw is mitigated. Add

    Related mechanism R2 Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this flaw is mitigated. Add

  • Some links cannot be passively tapped in Network taps and certifiers

    Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. 15 20

    Open question · Significant · Open. On the record

  • Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

    Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. 15

    Open question · Significant · Open. On the record

  • Residual side channels in simple passive setups in Network taps and certifiers

    Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. 5

    Theoretical argument · Significant · Open. On the record

  • Completeness rests on physical monitoring left out of scope in Network taps and certifiers

    The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. 14

    Open question · Significant · Open. On the record

    Related mechanism R1 Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this flaw is mitigated. Add

Possible additions3 for open flaws · 5 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

    • Bears on the open significant flaw “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
    • Network taps and certifiers waits on it. Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
    • Bears on the open significant flaw “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
    • Bears on the open significant flaw “Completeness rests on physical monitoring left out of scope” in Network taps and certifiers. Addresses the radio, power-line and thermal channels that network-level designs leave out.
    • Tamper evidence for verifier devices waits on it. There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist.
    • Network taps and certifiers waits on it. Radio, power-line and thermal channels are not addressed by network-level designs.
    • Tamper evidence for verifier devices waits on it. Memory wiping may use existing algorithms, but hardware testing is at an early stage.
    • Tamper evidence for verifier devices waits on it. A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
    • Tamper evidence for verifier devices depends on it.
    • Network taps and certifiers depends on it.
Dependencies4 missing prerequisites · 2 shared foundations · 11 blockers
Missing prerequisites
Shared foundations
Blockers
11 blockers recorded
  • Tamper evidence for verifier devices
    • A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. Performance & compatibility. Waits on Whole-workload recomputation (reproducible packets) 2
    • Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. Performance & compatibility. Waits on Network taps and certifiers 2
    • Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. Hardware trust. Waits on Tamper evidence for verifier devices 2 4
    • There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities 2
    • Memory wiping may use existing algorithms, but hardware testing is at an early stage. Coverage & hidden compute. Waits on Memory wiping and proofs of secure erasure 2
    • Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. Adversarial validation 2 4
  • Network taps and certifiers
    • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility 20 21
    • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference 14
    • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices 14 16
    • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities 14
    • Red-teaming by specialists is called for but has not been reported. Adversarial validation 14
What the verifier sees1 unspecified · 1 depend on design

From the family or selected implementation's record.

Model weights

Depends on the design for Network taps and certifiers.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Inputs and outputs

Depends on the design for Network taps and certifiers.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Training data

Depends on the design for Network taps and certifiers.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Exposure notes
Implementations3 systems
Tamper evidence for verifier devices
Network taps and certifiers
Sources21 cited
  1. Verification Plan, R. Dean (2026). Original
  2. Get Involved in Verification, AI Futures Project (2026). Original
  3. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). Original
  4. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
  5. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
  6. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
  7. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
  8. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). Original
  9. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). Original
  10. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). Original
  11. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). Original
  12. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). Original
  13. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). Original
  14. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
  15. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
  16. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
  17. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
  18. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
  19. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
  20. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
  21. Network Traffic Hashing, Amodo Design (2026). Original

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Filter mechanisms

Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.

All 25 mechanisms match.

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum readiness

How mature must each mechanism be?

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.

All claims

Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

All mechanisms

Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.

Start from a published design

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