Proposal Explorer

Add claims to see which ones the mechanisms address.

Built for an adversarial prover

Side-channel suppression for isolated facilities

No new hardware needed

On-chip telemetry from timing, memory and performance counters

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• On-chip telemetry from timing, memory and performance counters: Red-teamed

Open critical flaws

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{9 11}

  Theoretical argument · Critical · Open. On the record

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this flaw is mitigated. Add

Family findings

• Side-channel suppression for isolated facilities

  Context for AI 2040 inference-only verification stack. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

    Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ⁸

    Theoretical argument · Significant · Open. On the record

  • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

    Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ⁸

    Theoretical argument · Significant · Open. On the record

  • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

    The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ⁸

    Open question · Significant · Open. On the record

Open significant flaws

6 flaws in 2 mechanisms

• The recomputation server must be trusted in AI 2040 inference-only verification stack

  The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track. ^{1 2 4}

  Theoretical argument · Significant · Open. On the record

• Spare compute is not verified in AI 2040 inference-only verification stack

  The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs. ¹

  Theoretical argument · Significant · Open. On the record

• A recomputation family degrades against prompt-controlling adversaries in AI 2040 inference-only verification stack

  The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving. ^{1 2 6 7}

  Demonstrated attack · Significant · Open. On the record

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ¹¹

  Demonstrated attack · Significant · Open. On the record

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁹

  Theoretical argument · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{12 13}

  Theoretical argument · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁹

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open critical flaw “Software-read telemetry can be forged by the operator” in On-chip telemetry from timing, memory and performance counters. A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• R2 Tamper evidence for verifier devices Add
  • Side-channel suppression for isolated facilities waits on it. Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research.
• R1 Memory wiping and proofs of secure erasure Add
  • Side-channel suppression for isolated facilities waits on it. Memory wiping may use existing algorithms, but hardware testing is at an early stage.
• R1 Network taps and certifiers Add
  • Side-channel suppression for isolated facilities waits on it. Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated.
• R1 Whole-workload recomputation (reproducible packets) Add
  • Side-channel suppression for isolated facilities waits on it. A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
• R3 Sampled inference recomputation Add
  • Side-channel suppression for isolated facilities depends on it.
• R3 TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• R3 Sampled inference recomputation needed by Side-channel suppression for isolated facilities Add
• R1 Whole-workload recomputation (reproducible packets) needed by Side-channel suppression for isolated facilities Add
• R3 TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add

Blockers

10 blockers recorded

• Side-channel suppression for isolated facilities
  • A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. Performance & compatibility. Waits on Whole-workload recomputation (reproducible packets) ²
  • Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. Performance & compatibility. Waits on Network taps and certifiers ²
  • Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. Hardware trust. Waits on Tamper evidence for verifier devices ^{2 4}
  • There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ²
  • Memory wiping may use existing algorithms, but hardware testing is at an early stage. Coverage & hidden compute. Waits on Memory wiping and proofs of secure erasure ²
  • Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. Adversarial validation ^{2 4}
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{10 11}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{12 13}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ¹¹

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Side-channel suppression for isolated facilities

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

On-chip telemetry from timing, memory and performance counters

None on the map

1. Verification Plan, R. Dean (2026). Original
2. Get Involved in Verification, AI Futures Project (2026). Original
3. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). Original
4. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
5. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
6. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
7. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
8. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
9. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
10. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
11. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
12. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
13. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original