Proposal Explorer

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Bandwidth limits and compartmentalization

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Excluded by your filters: Chip registries and manufacturing records

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip registries and manufacturing records: Analysis · excluded by filters
• Bandwidth limits and compartmentalization: Analysis

Excluded by your filters

• Chip registries and manufacturing records Development status: Proposed. Minimum: Research demonstration.

Open significant failures

3 failures in 2 mechanisms

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ²

  Known failure · Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ⁷

  Known failure · Theoretical argument · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹⁰

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{3 5}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ³

  Scope limitation · Theoretical argument. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ⁷

  Scope limitation · Theoretical argument. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ⁷

  Scope limitation · Open question. On the record

Open questions

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{7 11 12}

  Open question · Theoretical argument. On the record

Not yet demonstrated

Proposed Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• Proposed Network taps and certifiers Add

  Excluded by filters: development: Proposed

  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.

Missing prerequisites

• Research demo Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Blockers

7 blockers recorded

• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{1 2}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{1 2 3}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{3 5}
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ⁷
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ⁸
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{7 10}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{7 11 12}

From the family or selected implementation's record. ?

Model weights

Not involved: Chip registries and manufacturing records and Bandwidth limits and compartmentalization.

Inputs and outputs

Not involved: Chip registries and manufacturing records and Bandwidth limits and compartmentalization.

Training data

Not involved: Chip registries and manufacturing records and Bandwidth limits and compartmentalization.

Chip registries and manufacturing records

None on the map

Bandwidth limits and compartmentalization

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

1. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
2. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
3. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
4. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
5. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
6. Verification Plan, R. Dean (2026). Original
7. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
8. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
9. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
10. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
11. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
12. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original