Proposal Explorer

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Built for an adversarial prover

Sampled inference recomputation and Side-channel suppression for isolated facilities

No new hardware needed

On-chip telemetry from timing, memory and performance counters

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Side-channel suppression for isolated facilities: Analysis

Family findings

• Sampled inference recomputation

  Context for AI 2040 inference-only verification stack. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

    Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. ^{11 12 13}

    Known failure · Demonstrated attack · Significant · Open. On the record

    Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this failure is mitigated. Add

  • Only recorded traffic is checked in Sampled inference recomputation

    Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. ^{11 14}

    Scope limitation · Theoretical argument. On the record

    Related mechanism Proposed Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this failure is mitigated. Add

  • Some inference optimizations are not covered in Sampled inference recomputation

    TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. ^{15 16}

    Known failure · Theoretical argument · Significant · Open. On the record

  • Mixed hardware widens the honest baseline in Sampled inference recomputation

    When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. ¹⁶

    Known failure · Open question · Minor · Open. On the record

Open significant failures

3 failures in 2 mechanisms

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ³

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• A recomputation family degrades against prompt-controlling adversaries in AI 2040 inference-only verification stack

  The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving. ^{6 7 11 12}

  Known failure · Demonstrated attack · Significant · Open. On the record

Scope limitations

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{1 3}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹

  Scope limitation · Theoretical argument. On the record

• The recomputation server must be trusted in AI 2040 inference-only verification stack

  The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track. ^{6 7 9}

  Scope limitation · Theoretical argument. On the record

• Spare compute is not verified in AI 2040 inference-only verification stack

  The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs. ⁶

  Scope limitation · Theoretical argument. On the record

• Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

  Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ¹⁷

  Scope limitation · Theoretical argument. On the record

Open questions

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹

  Open question · Open question. On the record

• Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

  Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ¹⁷

  Open question · Theoretical argument. On the record

• Inspection assumptions may not hold in Side-channel suppression for isolated facilities

  The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ¹⁷

  Open question · Open question. On the record

Not yet demonstrated

Proposed Sampled inference recomputation and Proposed Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Tamper evidence for verifier devices Add
  • Sampled inference recomputation waits on it. Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Proposed Memory wiping and proofs of secure erasure Add
  • Sampled inference recomputation waits on it. Memory wiping may use existing algorithms, but hardware testing is at an early stage.
• Proposed Network taps and certifiers Add
  • Sampled inference recomputation waits on it. Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated.
• Proposed Whole-workload recomputation (reproducible packets) Add
  • Sampled inference recomputation waits on it. A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
• Operational use TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add
• Proposed Whole-workload recomputation (reproducible packets) needed by Sampled inference recomputation Add

Blockers

12 blockers recorded

• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{2 3}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{4 5}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ³
• Sampled inference recomputation
  • A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. Performance & compatibility. Waits on Whole-workload recomputation (reproducible packets) ⁷
  • Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. Performance & compatibility. Waits on Network taps and certifiers ⁷
  • Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. Hardware trust. Waits on Tamper evidence for verifier devices ^{7 9}
  • There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ⁷
  • Memory wiping may use existing algorithms, but hardware testing is at an early stage. Coverage & hidden compute. Waits on Memory wiping and proofs of secure erasure ⁷
  • Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. Adversarial validation ^{7 9}
• Side-channel suppression for isolated facilities
  • No prototype or red-team exists; the design is a first-pass viability study. Adversarial validation ¹⁷
  • Volume costs of TEMPEST-grade power-line filters are uncertain, because existing products are mostly made to order. Performance & compatibility ¹⁷

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Side-channel suppression for isolated facilities.

Unspecified for Sampled inference recomputation. Check the implementation record.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Side-channel suppression for isolated facilities.

Unspecified for Sampled inference recomputation. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Side-channel suppression for isolated facilities.

Unspecified for Sampled inference recomputation. Check the implementation record.

On-chip telemetry from timing, memory and performance counters

None on the map

Sampled inference recomputation

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Research demo DiFR (Divergence From Reference) Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)
• Operational use TOPLOC Open-source project, Prime Intellect

Side-channel suppression for isolated facilities

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
3. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
4. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
5. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
6. Verification Plan, R. Dean (2026). Original
7. Get Involved in Verification, AI Futures Project (2026). Original
8. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). Original
9. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
10. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
11. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
12. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
13. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
14. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
15. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
16. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original
17. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original