Proposal Explorer

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Timed challenge-response and memory-occupation challenges and Bandwidth limits and compartmentalization

No new hardware needed

Timed challenge-response and memory-occupation challenges and On-chip telemetry from timing, memory and performance counters

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Timed challenge-response and memory-occupation challenges, GPU contention probes: Analysis
• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Bandwidth limits and compartmentalization: Analysis

Family findings

• Timed challenge-response and memory-occupation challenges

  Context for GPU contention probes. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Timing-based software attestation has been broken in practice in Timed challenge-response and memory-occupation challenges

    Castelluccia et al. implemented two generic attacks, one based on a return-oriented rootkit and one on code compression, together with specific attacks on SWATT and ICE-based schemes, on commodity sensor nodes. They conclude that secure time-based attestation is "very difficult, if not impossible, to design correctly". The attacks target embedded schemes, not AI accelerators. ^{2 3}

    Response: Perrig and van Doorn, two of the designers of SWATT and ICE, replied in August 2010. They argue that the rootkit attack defeats a naive implementation, not a property the schemes claim, and that the SWATT attack was run on a re-implementation on a chip with eight times the program memory, where SWATT's own chip is almost always full of code. They accept that the attack on ICE works.

    Known failure · Demonstrated attack · Significant · Disputed. On the record

  • Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

    Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ⁴

    Known failure · Theoretical argument · Significant · Open. On the record

    Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. In the proposal.

  • Error rates not quantified in Timed challenge-response and memory-occupation challenges

    Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ¹

    Open question · Open question. On the record

Open significant failures

4 failures in 2 mechanisms

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ⁶

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{7 8}

  Known failure · Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ¹⁰

  Known failure · Theoretical argument · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹²

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Answers are not tied to one GPU in GPU contention probes

  The paper's floating-point fingerprint characterises a GPU model. The authors state that it does not distinguish individual GPUs, so a probe answer does not show which device of that model produced it. ¹

  Scope limitation · Theoretical argument. On the record

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{1 6}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹

  Scope limitation · Theoretical argument. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ¹⁰

  Scope limitation · Theoretical argument. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ¹⁰

  Scope limitation · Open question. On the record

Open questions

• Error rates not quantified in GPU contention probes

  Monfared et al. show timing distributions that shift under contention, but leave hardware-specific thresholds to future work and state that false-positive and false-negative rates are not quantified. ¹

  Open question · Open question. On the record

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹

  Open question · Open question. On the record

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{10 13 14}

  Open question · Theoretical argument. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Proposed Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
• Operational use TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add
• Research demo Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Blockers

10 blockers recorded

• Timed challenge-response and memory-occupation challenges
  • Continuous probes add power draw, occupy GPU memory and reduce inference throughput. Performance & compatibility ¹
  • The paper gives an acceptance rule but no hardware-specific threshold values or measured error rates, so it does not settle when a timing shift counts as a detection. Adversarial validation ¹
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{5 6}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{7 8}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ⁶
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ¹⁰
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ⁴
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{10 12}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{10 13 14}

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Bandwidth limits and compartmentalization.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Bandwidth limits and compartmentalization.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Bandwidth limits and compartmentalization.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

On-chip telemetry from timing, memory and performance counters

None on the map

Bandwidth limits and compartmentalization

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
3. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
6. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
7. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
8. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
9. Verification Plan, R. Dean (2026). Original
10. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
11. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
12. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
13. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
14. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original