Proposal Explorer

Add claims to see which ones the mechanisms address.

Built for an adversarial prover

Bounding unexplained information in outputs and Tamper evidence for verifier devices

No new hardware needed

On-chip telemetry from timing, memory and performance counters

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Bounding unexplained information in outputs: Independent red-team

Family findings

• Tamper evidence for verifier devices

  Context for AI 2040 inference-only verification stack. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Seals are often defeated with simple methods in Tamper evidence for verifier devices

    Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor.

    In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones. ^{16 17}

    Known failure · Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

  • Security depends on inspection protocols in Tamper evidence for verifier devices

    An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier.

    Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated. ^{17 18}

    Scope limitation · Theoretical argument · Mechanism-class evidence. On the record

  • Attack classes outside published models in Tamper evidence for verifier devices

    The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure.

    The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure. ^{19 20 21}

    Known failure · Open question · Significant · Open · Mechanism-class evidence. On the record

Open significant failures

4 failures in 3 mechanisms

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ³

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{7 8}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this failure is mitigated. Add

• A recomputation family degrades against prompt-controlling adversaries in AI 2040 inference-only verification stack

  The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving. ^{7 8 11 12}

  Known failure · Demonstrated attack · Significant · Open. On the record

Scope limitations

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{1 3}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹

  Scope limitation · Theoretical argument. On the record

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{6 9}

  Scope limitation · Theoretical argument. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{7 10}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this failure is mitigated. Add

• The recomputation server must be trusted in AI 2040 inference-only verification stack

  The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track. ^{11 12 14}

  Scope limitation · Theoretical argument. On the record

• Spare compute is not verified in AI 2040 inference-only verification stack

  The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs. ¹¹

  Scope limitation · Theoretical argument. On the record

Open questions

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹

  Open question · Open question. On the record

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ⁶

  Open question · Open question. On the record

Not yet demonstrated

Proposed Tamper evidence for verifier devices

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Prompt-controlled entropy inflation widens the covert channel” in Bounding unexplained information in outputs. Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.
  • Bounding unexplained information in outputs waits on it. Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata.
• Research demo Bandwidth limits and compartmentalization Add
  • Bounding unexplained information in outputs waits on it. The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Proposed Memory wiping and proofs of secure erasure Add
  • Tamper evidence for verifier devices waits on it. Memory wiping may use existing algorithms, but hardware testing is at an early stage.
• Proposed Network taps and certifiers Add
  • Tamper evidence for verifier devices waits on it. Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated.
  • Bounding unexplained information in outputs depends on it.
• Proposed Side-channel suppression for isolated facilities Add
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
  • Tamper evidence for verifier devices waits on it. There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist.
• Proposed Whole-workload recomputation (reproducible packets) Add
  • Tamper evidence for verifier devices waits on it. A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
• Operational use Sampled inference recomputation Add
  • Bounding unexplained information in outputs depends on it.
  • Tamper evidence for verifier devices depends on it.
• Operational use TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add
• Operational use Sampled inference recomputation needed by Bounding unexplained information in outputs and Tamper evidence for verifier devices Add
• Research demo Bandwidth limits and compartmentalization needed by Bounding unexplained information in outputs Add
• Proposed Side-channel suppression for isolated facilities needed by Bounding unexplained information in outputs Add
• Proposed Network taps and certifiers needed by Bounding unexplained information in outputs Add
• Proposed Whole-workload recomputation (reproducible packets) needed by Tamper evidence for verifier devices Add

Shared foundations

• Sampled inference recomputation relied on by Bounding unexplained information in outputs and Tamper evidence for verifier devices
• Side-channel suppression for isolated facilities relied on by Bounding unexplained information in outputs and Tamper evidence for verifier devices
• Network taps and certifiers relied on by Bounding unexplained information in outputs and Tamper evidence for verifier devices

Blockers

15 blockers recorded

• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{2 3}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{4 5}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ³
• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ⁶
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{7 10}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{8 10}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ⁶
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ⁶
• Tamper evidence for verifier devices
  • A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. Performance & compatibility. Waits on Whole-workload recomputation (reproducible packets) ¹²
  • Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. Performance & compatibility. Waits on Network taps and certifiers ¹²
  • Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. Hardware trust. Waits on Tamper evidence for verifier devices ^{12 14}
  • There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹²
  • Memory wiping may use existing algorithms, but hardware testing is at an early stage. Coverage & hidden compute. Waits on Memory wiping and proofs of secure erasure ¹²
  • Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. Adversarial validation ^{12 14}

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters and Bounding unexplained information in outputs.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters and Bounding unexplained information in outputs.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Bounding unexplained information in outputs.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

On-chip telemetry from timing, memory and performance counters

None on the map

Bounding unexplained information in outputs

None on the map

Tamper evidence for verifier devices

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
3. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
4. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
5. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
6. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
7. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
8. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
9. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
10. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
11. Verification Plan, R. Dean (2026). Original
12. Get Involved in Verification, AI Futures Project (2026). Original
13. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). Original
14. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
15. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
16. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). Original
17. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). Original
18. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). Original
19. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). Original
20. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). Original
21. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). Original