Proposal Explorer

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Excluded by your filters: Chip location verification and Hardware-attested weight binding

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip location verification, Lucid sovereignty (location) certificates: Analysis · excluded by filters
• Hardware-attested weight binding: Independent red-team · excluded by filters

Excluded by your filters

• Chip location verification Assumes a semi-trusted prover; the filter asks for a prover classified as adversarial.
• Hardware-attested weight binding Assumes a semi-trusted prover; the filter asks for a prover classified as adversarial.

Open critical failures

• Underlying attestation can be forged or relayed in Hardware-attested weight binding

  Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{9 10 14 15 16 17}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Family findings

• Chip location verification

  Context for Lucid sovereignty (location) certificates. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Extracting a chip's key lets another device answer for it in Chip location verification

    Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{5 6}

    Known failure · Theoretical argument · Significant · Open. On the record

  • Added delay can shift an estimated position in Chip location verification

    Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{6 7}

    Known failure · Demonstrated attack · Significant · Open. On the record

  • Faster-than-assumed network paths in Chip location verification

    Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{6 7}

    Known failure · Theoretical argument · Significant · Open. On the record

  • Compromised landmarks can falsify measurements in Chip location verification

    A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 6 7}

    Known failure · Theoretical argument · Significant · Open. On the record

Open significant failures

2 failures in 1 mechanism

• On-chip keys may be extractable in Lucid sovereignty (location) certificates

  Tee and Happel argue that ping-based location protocols backed by keys stored on the chip can be compromised if an adversary with physical access extracts those keys. In this specification, the evidence chain rests on the hardware root of trust's signed quote, whose signing key must be protected by the hardware. ^{1 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• General delay and landmark attacks apply in Lucid sovereignty (location) certificates

  Attacks on delay-based location verification in general also apply. Brass and Aarne discuss adding delay, using faster paths such as dark fibre, and compromising landmarks. The specification counters anchor impersonation with a signed anchor directory. Against collusion it recommends anchors in diverse places run by several independent operators, and peer monitoring that temporarily removes anchors whose timings deviate. ^{1 6}

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Physical attacks on the trusted hardware are out of scope in Lucid sovereignty (location) certificates

  The specification places the hardware root of trust and the TEE in the trusted computing base. It assumes they resist software attacks, notes that the attacker may have physical access, and leaves sophisticated physical attacks, such as bus probing and side-channel analysis, as a residual risk. It says that future revisions may add requirements for physical tamper evidence. ¹

  Scope limitation · Theoretical argument. On the record

• For private models, a user can confirm consistency but not content in Hardware-attested weight binding

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{8 19}

  Scope limitation · Open question. On the record

Not yet demonstrated

Proposed Chip location verification

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
• Operational use TEE remote attestation for AI workloads Add

  Excluded by filters: assumes a semi-trusted prover

  • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.
  • Chip location verification depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Chip location verification and Hardware-attested weight binding Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Chip location verification and Hardware-attested weight binding

Blockers

3 blockers recorded

• Chip location verification
  • The specification is an unfinished draft with no public implementation or evaluation. Adversarial validation ^{1 2}
  • It needs a globally distributed, trusted anchor fleet and an endorser to run the anchor directory. Access & governance ¹
• Hardware-attested weight binding
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹⁴

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-attested weight binding.

Unspecified for Chip location verification. Check the implementation record.

Inputs and outputs

Unspecified for Chip location verification and Hardware-attested weight binding. Check the implementation record.

Training data

Not involved: Hardware-attested weight binding.

Unspecified for Chip location verification. Check the implementation record.

Chip location verification

• Proposed Lucid sovereignty (location) certificates Standard, Lucid Computing

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
2. Sovereignty Certificates Working Group (2026). Original
3. Lucid Computing: Verifiable AI. Proven in hardware. (2026). Original
4. Lucid Developer Platform documentation (2026). Original
5. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
6. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
7. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
8. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
9. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
10. A primer on secure enclaves, Tinfoil (2026). Original
11. Backend infrastructure, Tinfoil (2026). Original
12. How verification works in Tinfoil, Tinfoil (2026). Original
13. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
14. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
15. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
16. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
17. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
18. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
19. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original