Proposal Explorer

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Built for an adversarial prover

Side-channel suppression for isolated facilities and Timed challenge-response and memory-occupation challenges

No new hardware needed

On-chip telemetry from timing, memory and performance counters and Timed challenge-response and memory-occupation challenges

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Timed challenge-response and memory-occupation challenges: Analysis

Family findings

• Side-channel suppression for isolated facilities

  Context for AI 2040 inference-only verification stack. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

    Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ⁸

    Open question · Theoretical argument. On the record

  • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

    Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ⁸

    Scope limitation · Theoretical argument. On the record

  • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

    The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ⁸

    Open question · Open question. On the record

Open significant failures

4 failures in 3 mechanisms

• A recomputation family degrades against prompt-controlling adversaries in AI 2040 inference-only verification stack

  The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving. ^{1 2 6 7}

  Known failure · Demonstrated attack · Significant · Open. On the record

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ¹¹

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{12 13}

  Known failure · Theoretical argument · Significant · Open. On the record

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ¹⁴

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. Add

Scope limitations

• The recomputation server must be trusted in AI 2040 inference-only verification stack

  The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track. ^{1 2 4}

  Scope limitation · Theoretical argument. On the record

• Spare compute is not verified in AI 2040 inference-only verification stack

  The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs. ¹

  Scope limitation · Theoretical argument. On the record

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{9 11}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁹

  Scope limitation · Theoretical argument. On the record

Open questions

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁹

  Open question · Open question. On the record

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ⁹

  Open question · Open question. On the record

Not yet demonstrated

Proposed Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Bandwidth limits and compartmentalization Add
  • Bears on the open significant failure “Remote memory narrows the timing margin” in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
  • Timed challenge-response and memory-occupation challenges waits on it. Outside help, such as remote memory, must be excluded during challenges.
• Research demo Tamper evidence for verifier devices Add
  • Side-channel suppression for isolated facilities waits on it. Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Proposed Memory wiping and proofs of secure erasure Add
  • Side-channel suppression for isolated facilities waits on it. Memory wiping may use existing algorithms, but hardware testing is at an early stage.
• Proposed Network taps and certifiers Add
  • Side-channel suppression for isolated facilities waits on it. Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated.
• Proposed Whole-workload recomputation (reproducible packets) Add
  • Side-channel suppression for isolated facilities waits on it. A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
• Operational use Sampled inference recomputation Add
  • Side-channel suppression for isolated facilities depends on it.
• Operational use TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• Operational use Sampled inference recomputation needed by Side-channel suppression for isolated facilities Add
• Proposed Whole-workload recomputation (reproducible packets) needed by Side-channel suppression for isolated facilities Add
• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add

Blockers

13 blockers recorded

• Side-channel suppression for isolated facilities
  • A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. Performance & compatibility. Waits on Whole-workload recomputation (reproducible packets) ²
  • Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. Performance & compatibility. Waits on Network taps and certifiers ²
  • Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. Hardware trust. Waits on Tamper evidence for verifier devices ^{2 4}
  • There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ²
  • Memory wiping may use existing algorithms, but hardware testing is at an early stage. Coverage & hidden compute. Waits on Memory wiping and proofs of secure erasure ²
  • Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. Adversarial validation ^{2 4}
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{10 11}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{12 13}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ¹¹
• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ¹⁴
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{9 14}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹⁴

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Side-channel suppression for isolated facilities

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

On-chip telemetry from timing, memory and performance counters

None on the map

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

1. Verification Plan, R. Dean (2026). Original
2. Get Involved in Verification, AI Futures Project (2026). Original
3. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). Original
4. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
5. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
6. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
7. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
8. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
9. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
10. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
11. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
12. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
13. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
14. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
15. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
16. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
17. Proofs of Space, S. Dziembowski et al. (2015). Original
18. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
19. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
20. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
21. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original