Proposal Explorer

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Built for an adversarial prover

Network taps and certifiers, Side-channel suppression for isolated facilities and Proofs of useful work for capacity accounting

No new hardware needed

Proofs of useful work for capacity accounting and Chip registries and manufacturing records

Flaws since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ¹

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Network taps and certifiers: Analysis
• Side-channel suppression for isolated facilities: Analysis
• Proofs of useful work for capacity accounting: Analysis
• Chip registries and manufacturing records: Analysis

Open significant flaws

14 flaws in 4 mechanisms

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{1 9}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R3 Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R2 Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this flaw is mitigated. Add

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{2 10}

  Open question · Significant · Open. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ²

  Open question · Significant · Open. On the record

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ⁵

  Theoretical argument · Significant · Open. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ¹

  Open question · Significant · Open. On the record

  Related mechanism R1 Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

  Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ¹¹

  Theoretical argument · Significant · Open. On the record

• Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

  Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ¹¹

  Theoretical argument · Significant · Open. On the record

• Inspection assumptions may not hold in Side-channel suppression for isolated facilities

  The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ¹¹

  Open question · Significant · Open. On the record

• Proves that work was done, not that no capacity remains in Proofs of useful work for capacity accounting

  Proof-of-work accounting bounds unmonitored compute only relative to an estimate of what the actor has. Attestable states that the verifier "needs a credible estimate of the compute available" to the actor, and that a proof "cannot discover a datacenter that was never declared". ¹²

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: A registry of chips is one basis for the estimate of available compute that the flaw's source says the verifier needs. A pointer, not evidence that this flaw is mitigated. In the proposal.

  Related mechanism R1 Remote detection of data centres: Looks for data centres that were never declared, which a proof cannot discover. A pointer, not evidence that this flaw is mitigated. Add

• Security rests on new hardness assumptions in Proofs of useful work for capacity accounting

  Komargodski and Weinstein base security on hardness assumptions about batches of low-rank random linear equations, and list PoUW "from more standard or well-studied assumptions" as an open problem. Pearl's floating-point variant introduces a further "quantized-subspace hardness" assumption. ^{14 15}

  Open question · Significant · Open. On the record

• Known shortcuts let a miner claim somewhat more work than it did in Proofs of useful work for capacity accounting

  Pearl's specification lists known mining speedups: crafted inputs, precision shortcuts, seed grinding, work reuse, and faster kernels or hardware. A policy check caps the summands a miner may skip at one-sixteenth of those in a tile. For capacity bounding, any gap between work proven and work possible leaves spare capacity. ¹⁵

  Theoretical argument · Significant · Open. On the record

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{19 21}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this flaw is mitigated. Add

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ¹⁸

  Theoretical argument · Significant · Open. On the record

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ¹⁹

  Theoretical argument · Significant · Open. On the record

Not yet demonstrated

R1 Network taps and certifiers, R1 Side-channel suppression for isolated facilities, R1 Proofs of useful work for capacity accounting and R1 Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 Deterministic and bit-exact inference Add
  • Bears on the open significant flaw “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  • Network taps and certifiers waits on it. Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
• R2 Bounding unexplained information in outputs Add
  • Bears on the open significant flaw “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
• R1 Remote detection of data centres Add
  • Bears on the open significant flaw “Proves that work was done, not that no capacity remains” in Proofs of useful work for capacity accounting. Looks for data centres that were never declared, which a proof cannot discover.
  • Bears on the open significant flaw “Records cover only chips that were recorded” in Chip registries and manufacturing records. Looks for large data centres that were never declared, which a registry cannot show.
• R2 Tamper evidence for verifier devices Add
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• R3 Sampled inference recomputation Add
  • Network taps and certifiers depends on it.

Missing prerequisites

• R3 Sampled inference recomputation needed by Network taps and certifiers Add
• R3 Deterministic and bit-exact inference needed by Network taps and certifiers Add
• R2 Tamper evidence for verifier devices needed by Network taps and certifiers Add

Blockers

13 blockers recorded

• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{10 22}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ¹
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{1 3}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ¹
• Side-channel suppression for isolated facilities
  • No prototype or red-team exists; the design is a first-pass viability study. Adversarial validation ¹¹
  • Volume costs of TEMPEST-grade power-line filters are uncertain, because existing products are mostly made to order. Performance & compatibility ¹¹
• Proofs of useful work for capacity accounting
  • Bounding spare capacity needs a credible estimate of the compute available to the actor, including third-party access. Capacity bounds ¹²
  • Proofs of work cannot find facilities that were never declared. Coverage & hidden compute ¹²
  • As of September 2026 no implementation, demonstration or independent evaluation of proofs of work for capacity bounding has been published. Adversarial validation
• Chip registries and manufacturing records
  • No AI chip registry operates, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{17 18}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{17 18 19}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{19 21}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Network taps and certifiers and Proofs of useful work for capacity accounting.

Not involved: Side-channel suppression for isolated facilities and Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for Network taps and certifiers and Proofs of useful work for capacity accounting.

Not involved: Side-channel suppression for isolated facilities and Chip registries and manufacturing records.

Training data

Depends on the design for Network taps and certifiers.

Not involved: Side-channel suppression for isolated facilities, Proofs of useful work for capacity accounting and Chip registries and manufacturing records.

Network taps and certifiers

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

Side-channel suppression for isolated facilities

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Proofs of useful work for capacity accounting

• R3 Pearl proof-of-useful-work blockchain Open-source project, Pearl Research Labs

Chip registries and manufacturing records

None on the map

1. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
2. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
3. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
4. Verification Plan, R. Dean (2026). Original
5. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
6. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
7. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
8. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
9. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
10. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
11. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
12. Pacing AI Requires Proof, Attestable (2026). Original
13. Mechanisms to Verify International Agreements About AI Development, A. Scher & L. Thiergart (2025). Original
14. Proofs of Useful Work from Arbitrary Matrix Multiplication, I. Komargodski & O. Weinstein (2025). Original
15. Pearl Floating Point Scheme Specification, Pearl Research Team (2026). Original
16. pearl: Monorepo for the Pearl network, Pearl Research Labs (2026). Original
17. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
18. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
19. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
20. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
21. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
22. Network Traffic Hashing, Amodo Design (2026). Original