Proposal Explorer

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Excluded by your filters: Memory wiping and proofs of secure erasure, Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Memory wiping and proofs of secure erasure: Analysis · excluded by filters
• Bandwidth limits and compartmentalization: Analysis · excluded by filters
• Timed challenge-response and memory-occupation challenges: Analysis · excluded by filters

Excluded by your filters

• Memory wiping and proofs of secure erasure Readiness R1 is below the minimum of R3.
• Bandwidth limits and compartmentalization Readiness R2 is below the minimum of R3.
• Timed challenge-response and memory-occupation challenges Readiness R2 is below the minimum of R3.

Open significant flaws

8 flaws in 3 mechanisms

• Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

  Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. ^{5 6}

  Open question · Significant · Open. On the record

• Outside help during challenges in Memory wiping and proofs of secure erasure

  Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. ^{3 4}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this flaw is mitigated. In the proposal.

  Related mechanism R2 Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{9 12 13}

  Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ⁹

  Theoretical argument · Significant · Open. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ⁹

  Theoretical argument · Significant · Open. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ⁹

  Open question · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹¹

  Theoretical argument · Significant · Open. On the record

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It adds that pre-staging data is ruled out only by unpredictable, capacity-filling challenges. ⁴

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this flaw is mitigated. In the proposal.

Open minor flaws

2 mechanisms with minor findings

• Gap between erased and total memory in Memory wiping and proofs of secure erasure

  Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. ³

  Theoretical argument · Minor · Open. On the record

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions but do not define thresholds or statistical tests, so false-positive and false-negative rates are not quantified. ¹⁴

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Memory wiping and proofs of secure erasure

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R2 Tamper evidence for verifier devices Add

  Excluded by filters: readiness R2

  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• R1 Network taps and certifiers Add

  Excluded by filters: readiness R1

  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.

Missing prerequisites

• R2 Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Blockers

10 blockers recorded

• Memory wiping and proofs of secure erasure
  • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility ^{4 5 6}
  • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ^{3 4}
  • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute ⁵
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ⁹
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ⁴
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{9 11}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{9 12 13}
• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ⁴
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{4 14}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ⁴

From the family or selected implementation's record. ?

Model weights

Not involved: Memory wiping and proofs of secure erasure, Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges.

Inputs and outputs

Not involved: Memory wiping and proofs of secure erasure, Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges.

Training data

Not involved: Memory wiping and proofs of secure erasure, Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges.

Memory wiping and proofs of secure erasure

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

Bandwidth limits and compartmentalization

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Timed challenge-response and memory-occupation challenges

• R1 Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• R2 GPU contention probes Research prototype
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R2 SAGE Research prototype
• R2 VRAM-residency challenge Research prototype

1. Verification Plan, R. Dean (2026). Original
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original
9. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
10. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
11. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
12. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
13. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
14. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
15. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
16. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
17. Proofs of Space, S. Dziembowski et al. (2015). Original
18. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
19. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original