Proposal Explorer

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Timed challenge-response and memory-occupation challenges, Bandwidth limits and compartmentalization and Remote detection of data centres

No new hardware needed

Timed challenge-response and memory-occupation challenges, Chip registries and manufacturing records and Remote detection of data centres

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Timed challenge-response and memory-occupation challenges: Analysis
• Chip registries and manufacturing records: Analysis
• Bandwidth limits and compartmentalization: Analysis
• Remote detection of data centres: Analysis

Open significant failures

4 failures in 3 mechanisms

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ¹

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. In the proposal.

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ¹²

  Known failure · Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ¹⁶

  Known failure · Theoretical argument · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹⁸

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{13 15}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. In the proposal.

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ¹³

  Scope limitation · Theoretical argument. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ¹⁶

  Scope limitation · Theoretical argument. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ¹⁶

  Scope limitation · Open question. On the record

• Facilities can be disguised or hidden in Remote detection of data centres

  Halstead and Larsen discuss two ways to hide a facility. One is to disguise it as a legitimate industrial site. The other is to build it underground, with cooling that avoids visible heat plumes. They note that the underground option requires bespoke engineering. ¹⁵

  Scope limitation · Theoretical argument. On the record

• Small sites may not be detectable in Remote detection of data centres

  Halstead and Larsen conclude that a sufficiently small covert project could not be ruled out with confidence. In their estimates, the chance of detection is lower for smaller sites. Krawec notes that small data centres in existing buildings may lack the distinctive features of large facilities. ^{15 21}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Accounts for chips from the fab onwards, which does not depend on a site being visible. A pointer, not evidence that this failure is mitigated. In the proposal.

Open questions

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ³

  Open question · Open question. On the record

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{16 19 20}

  Open question · Theoretical argument. On the record

• Search for unknown sites is undemonstrated in Remote detection of data centres

  Krawec reports that telling data centres apart from other industrial facilities systematically is difficult. Automating detection would need large amounts of training imagery and a purpose-trained model. In Krawec's words, automated data-centre detection "remains primarily conceptual at present". ²¹

  Open question · Open question. On the record

Not yet demonstrated

Proposed Chip registries and manufacturing records and Proposed Remote detection of data centres

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• Proposed Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.

Missing prerequisites

• Research demo Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Blockers

13 blockers recorded

• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ¹
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{1 3}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{11 12}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{11 12 13}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{13 15}
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ¹⁶
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ¹
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{16 18}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{16 19 20}
• Remote detection of data centres
  • Wide-area, automated detection of data centres is not yet practical and needs large training datasets. Coverage & hidden compute ²¹
  • No measured detection or false-alarm rates for finding undeclared facilities have been published. Adversarial validation ^{15 21}
  • Recent high-resolution imagery is costly, is limited by weather and needs trained analysts. Access & governance ²¹

From the family or selected implementation's record. ?

Model weights

Not involved: Timed challenge-response and memory-occupation challenges, Chip registries and manufacturing records, Bandwidth limits and compartmentalization and Remote detection of data centres.

Inputs and outputs

Not involved: Timed challenge-response and memory-occupation challenges, Chip registries and manufacturing records, Bandwidth limits and compartmentalization and Remote detection of data centres.

Training data

Not involved: Timed challenge-response and memory-occupation challenges, Chip registries and manufacturing records, Bandwidth limits and compartmentalization and Remote detection of data centres.

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

Chip registries and manufacturing records

None on the map

Bandwidth limits and compartmentalization

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

Remote detection of data centres

None on the map

1. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
2. Verification Plan, R. Dean (2026). Original
3. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
4. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
5. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
6. Proofs of Space, S. Dziembowski et al. (2015). Original
7. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
8. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
9. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
10. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original
11. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
12. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
13. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
14. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
15. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
16. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
17. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
18. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
19. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
20. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
21. Tracking Hyperscale AI Data Center Growth with Satellite Imagery, C. Krawec (2026). Original
22. Introducing the Frontier Data Centers Hub, Epoch AI (2025). Original
23. AI Data Centers Documentation – Methodology, Epoch AI (2026). Original