Proposal Explorer

Add claims to see which ones the mechanisms address.

Not counted

Excluded by your filters: Chip location verification, On-chip telemetry from timing, memory and performance counters and Hardware-enabled guarantees (flexHEG) and guarantee processors

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Chip location verification: Analysis · excluded by filters
• On-chip telemetry from timing, memory and performance counters: Red-teamed · excluded by filters
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis · excluded by filters

Excluded by your filters

• Chip location verification Attack testing is analysis; the filter asks for at least independent red-team.
• On-chip telemetry from timing, memory and performance counters Attack testing is red-teamed; the filter asks for at least independent red-team.
• Hardware-enabled guarantees (flexHEG) and guarantee processors Attack testing is analysis; the filter asks for at least independent red-team.

Open critical flaws

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{8 10}

  Theoretical argument · Critical · Open. On the record

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this flaw is mitigated. In the proposal.

Open significant flaws

13 flaws in 3 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Theoretical argument · Significant · Open. On the record

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ¹⁰

  Demonstrated attack · Significant · Open. On the record

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁸

  Theoretical argument · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{11 12}

  Theoretical argument · Significant · Open. On the record

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{14 16}

  Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{13 15}

  Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{14 15}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this flaw is mitigated. Add

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{13 15}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R1 Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws

1 mechanism with minor findings

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁸

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Chip location verification and R1 Hardware-enabled guarantees (flexHEG) and guarantee processors

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 TEE remote attestation for AI workloads Add
  • Chip location verification depends on it.
  • On-chip telemetry from timing, memory and performance counters depends on it.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
• R1 Chip registries and manufacturing records Add

  Excluded by filters: attack testing: analysis

  • Bears on the open significant flaw “Supply-chain diversion and hidden backdoors” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
• R1 Remote detection of data centres Add

  Excluded by filters: attack testing: analysis

  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
• R2 Tamper evidence for verifier devices Add

  Excluded by filters: attack testing: analysis

  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Chip location verification, On-chip telemetry from timing, memory and performance counters and Hardware-enabled guarantees (flexHEG) and guarantee processors Add
• R1 Chip registries and manufacturing records needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Chip location verification, On-chip telemetry from timing, memory and performance counters and Hardware-enabled guarantees (flexHEG) and guarantee processors

Blockers

13 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 18}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{9 10}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{11 12}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁸
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ¹⁰
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ¹⁴
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{14 16}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{13 15}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ¹³
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ¹⁵

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Chip location verification.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Chip location verification.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Chip location verification.

Chip location verification

• R1 Lucid sovereignty (location) certificates Standard, Lucid Computing

On-chip telemetry from timing, memory and performance counters

None on the map

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
9. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
10. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
11. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
12. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
13. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
14. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
15. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
16. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
17. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original
18. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original