Proposal Explorer

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Side-channel suppression for isolated facilities, Chip location verification and Hardware-enabled guarantees (flexHEG) and guarantee processors

No new hardware needed

Chip location verification and Chip registries and manufacturing records

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Side-channel suppression for isolated facilities: Analysis
• Chip location verification: Analysis
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis
• Chip registries and manufacturing records: Analysis

Open significant failures

8 failures in 3 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{2 7}

  Known failure · Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{2 5}

  Known failure · Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{2 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{2 5 6}

  Known failure · Theoretical argument · Significant · Open. On the record

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{10 12}

  Known failure · Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ¹⁰

  Known failure · Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ¹⁰

  Known failure · Theoretical argument · Significant · Open. On the record

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ⁵

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

  Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ¹

  Scope limitation · Theoretical argument. On the record

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{9 11}

  Scope limitation · Theoretical argument. On the record

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{9 11}

  Scope limitation · Open question. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this failure is mitigated. In the proposal.

  Related mechanism Proposed Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this failure is mitigated. Add

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{15 17}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ¹⁵

  Scope limitation · Theoretical argument. On the record

Open questions

• Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

  Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ¹

  Open question · Theoretical argument. On the record

• Inspection assumptions may not hold in Side-channel suppression for isolated facilities

  The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ¹

  Open question · Open question. On the record

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{10 11}

  Open question · Open question. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this failure is mitigated. In the proposal.

Not yet demonstrated

Proposed Side-channel suppression for isolated facilities, Proposed Chip location verification, Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors and Proposed Chip registries and manufacturing records

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Tamper evidence for verifier devices Add
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
• Operational use TEE remote attestation for AI workloads Add
  • Chip location verification depends on it.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Chip location verification and Hardware-enabled guarantees (flexHEG) and guarantee processors Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Chip location verification and Hardware-enabled guarantees (flexHEG) and guarantee processors

Blockers

14 blockers recorded

• Side-channel suppression for isolated facilities
  • No prototype or red-team exists; the design is a first-pass viability study. Adversarial validation ¹
  • Volume costs of TEMPEST-grade power-line filters are uncertain, because existing products are mostly made to order. Performance & compatibility ¹
• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{3 4}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{2 7 16}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ²
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{2 5}
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ¹⁰
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{10 12}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{9 11}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ⁹
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ¹¹
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{5 14}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{5 14 15}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{15 17}

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Side-channel suppression for isolated facilities, Chip location verification and Chip registries and manufacturing records.

Inputs and outputs

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Side-channel suppression for isolated facilities, Chip location verification and Chip registries and manufacturing records.

Training data

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Not involved: Side-channel suppression for isolated facilities, Chip location verification and Chip registries and manufacturing records.

Side-channel suppression for isolated facilities

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

Chip location verification

• Proposed Lucid sovereignty (location) certificates Standard, Lucid Computing

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

Chip registries and manufacturing records

None on the map

1. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
2. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
3. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
4. Ping-based Location, Ulyssean (2025). Original
5. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
6. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
7. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
8. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
9. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
10. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
11. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
12. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
13. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original
14. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
15. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
16. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
17. Covert AI Projects, B. Halstead & T. Larsen (2026). Original