Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Hardware-attested weight binding for hardware-attested weight binding showing users that a service runs its committed weights

Built for an adversarial prover

Chip location verification and Bandwidth limits and compartmentalization

No new hardware needed

Chip location verification and Hardware-attested weight binding

Failures since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Hardware-attested weight binding ^{15 25}

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip location verification: Analysis
• Bandwidth limits and compartmentalization: Analysis
• Hardware-attested weight binding: Independent red-team

Open critical failures

• Underlying attestation can be forged or relayed in Hardware-attested weight binding

  Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{16 17 21 22 23 24}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Open significant failures

6 failures in 2 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Known failure · Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Known failure · Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Known failure · Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ⁹

  Known failure · Theoretical argument · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹²

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ⁹

  Scope limitation · Theoretical argument. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ⁹

  Scope limitation · Open question. On the record

• For private models, a user can confirm consistency but not content in Hardware-attested weight binding

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{15 26}

  Scope limitation · Open question. On the record

Open questions

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{9 13 14}

  Open question · Theoretical argument. On the record

Not yet demonstrated

Proposed Chip location verification

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use TEE remote attestation for AI workloads Add
  • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.
  • Chip location verification depends on it.
• Research demo Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• Proposed Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: needs new chips

  • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Chip location verification and Hardware-attested weight binding Add
• Research demo Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Chip location verification and Hardware-attested weight binding

Blockers

9 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 27}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ⁹
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ¹⁰
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{9 12}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{9 13 14}
• Hardware-attested weight binding
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ²¹

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-attested weight binding.

Not involved: Chip location verification and Bandwidth limits and compartmentalization.

Inputs and outputs

Not involved: Chip location verification and Bandwidth limits and compartmentalization.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Training data

Not involved: Chip location verification, Bandwidth limits and compartmentalization and Hardware-attested weight binding.

Chip location verification

• Proposed Lucid sovereignty (location) certificates Standard, Lucid Computing

Bandwidth limits and compartmentalization

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Verification Plan, R. Dean (2026). Original
9. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
10. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
11. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
12. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
13. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
14. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
15. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
16. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
17. A primer on secure enclaves, Tinfoil (2026). Original
18. Backend infrastructure, Tinfoil (2026). Original
19. How verification works in Tinfoil, Tinfoil (2026). Original
20. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
21. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
22. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
23. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
24. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
25. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
26. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
27. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original