Proposal Explorer

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In production

• R3 TEE remote attestation for AI workloads for showing users which software serves their AI requests, not which model

Built for an adversarial prover

Chip location verification

No new hardware needed

Chip location verification and TEE remote attestation for AI workloads

Flaws since mitigated

• Tampered node configuration passed attestation in TEE remote attestation for AI workloads ^{12 13}

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Chip location verification: Analysis
• TEE remote attestation for AI workloads, Apple Private Cloud Compute: Independent red-team

Family findings

• TEE remote attestation for AI workloads

  Context for Apple Private Cloud Compute. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • DDR5 memory-bus interposers forge Intel TDX attestations and break SEV-SNP protections (TEE.fail, DDRop) in TEE remote attestation for AI workloads

    Critical when the verifier must resist physical access plus host control on the affected DDR5 platforms. The Intel demonstrations defeat attestation; TEE.fail's AMD demonstration extracts a guest key, not an AMD attestation key. These results do not cover every TEE architecture.

    Independent researchers placed an interposer, built for under $1000, on the DDR5 memory bus of servers running Intel TDX and AMD SEV-SNP. Server TEEs encrypt memory deterministically, without integrity or freshness protection, and the researchers exploited this to recover secrets. The attack needs physical access and root privileges.

    • On Intel, they extracted the provisioning certification key from a machine that Intel's service rated fully up to date. This per-CPU key signs the keys used in SGX and TDX attestation. With it they forged SGX and TDX attestations.
    • On AMD SEV-SNP with ciphertext hiding enabled, they recovered an ECDSA private key used by OpenSSL inside the virtual machine. It was not an AMD attestation key. Other independent attacks did break SEV-SNP attestation. Battering RAM did so with a DDR4 interposer, and RMPocalypse and Fabricked from malicious host software.

    A second team, from KU Leuven, ETH Zurich, Durham University and Google, built DDRop, an active DDR5 interposer with a bill of materials of $159. It silently drops memory writes, which memory encryption without freshness protection cannot detect. With brief physical access and control of the host software and BIOS, the researchers forced trust domains into debug mode and forged attestation reports on an up-to-date Intel TDX platform. The same primitive breaks the integrity of Scalable SGX and SEV-SNP, though the authors report no SEV-SNP attestation forgery.

    The TEE.fail authors report that Intel and AMD consider interposer attacks out of scope, which leaves physical security as the only mitigation. The DDRop authors report the same position, and that both vendors issued security advisories on disclosure in September 2026. PAL*M lists this attack class as out of its scope, and Tinfoil's documentation acknowledges it. Gloria Z calls key extraction through bus interposition "relatively low-hanging fruit" in an international treaty scenario. ^{14 15 16 17 18 19 20 21}

    Demonstrated attack · Critical · Open · Mechanism-class evidence. On the record · Also listed on Apple Private Cloud Compute

    Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

  • DDR4 memory-bus interposers forge SGX and SEV-SNP attestation (Battering RAM, WireTap) in TEE remote attestation for AI workloads

    Critical for the tested DDR4 SGX and SEV-SNP configurations against a physical host attacker. The authors exclude DDR5 from these demonstrations, including TDX servers; the DDR5 attacks have a separate finding.

    Two independent teams broke server TEE attestation on DDR4 memory with interposers they built themselves. Both attacks need physical access to install the device and root privileges on the host.

    • Battering RAM, by researchers at KU Leuven and the Universities of Birmingham and Durham, uses an interposer with a bill of materials of $47.62. It creates memory aliases at runtime, which bypasses the boot-time alias checks that AMD and Intel introduced against static aliasing attacks such as BadRAM. On Intel Scalable SGX it gained arbitrary read and write access to enclave plaintext and extracted SGX's platform provisioning key, which lets an attacker forge attestation certificates for arbitrary quoting enclaves. On up-to-date AMD SEV-SNP servers it captured the launch digests of genuine VMs and replayed them into modified VMs, so that backdoored VMs pass attestation.
    • WireTap, by researchers at Purdue University and Georgia Tech, uses an interposer built for under $1000 that records DDR4 bus traffic. On a Xeon Scalable server in fully trusted status it recovered the ECDSA attestation key of SGX's Quoting Enclave in 45 minutes and forged SGX quotes. The authors then showed end-to-end attacks on SGX-based blockchain deployments.

    Both attacks are limited to DDR4 systems. The Battering RAM authors state that all commercial TDX machines use DDR5, and the WireTap authors state that 4th and 5th generation Xeon Scalable processors need DDR5 and are not affected by their current work. According to the Battering RAM authors, Intel and AMD acknowledged the findings but consider physical attacks on DRAM out of scope for their current products. The WireTap authors report that Intel considers their attack outside the SGX threat model, and that there is no mitigation besides running servers in secure physical environments. ^{19 22}

    Demonstrated attack · Critical · Open · Mechanism-class evidence. On the record

    Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

  • Software-only forgery of SEV-SNP attestation (RMPocalypse, Fabricked) in TEE remote attestation for AI workloads

    Critical on affected SEV-SNP platforms before the vendor fixes. These attacks need privileged host software, not physical access. Mitigated records AMD's released updates; it does not establish that a particular deployment installed or enforces them.

    Researchers at ETH Zurich showed that a malicious hypervisor can corrupt the Reverse Map Table (RMP) while SEV-SNP initialises it. SEV-SNP uses the RMP to store security metadata for every DRAM page, and a single 8-byte overwrite leaves the whole table compromised. The attack needs no physical access. The authors confirmed it on Zen 3, Zen 4 and Zen 5 processors and state that it affects all AMD processors that support SEV-SNP. They demonstrated forged attestation values, debugging enabled on production confidential VMs, reads and writes of encrypted VM memory, and replay of VM register state.

    AMD assigned CVE-2025-0033. Its bulletin rates the issue medium severity and reports SEV firmware, microcode or platform firmware updates for every affected EPYC server and embedded series, with release dates from June 2025 to February 2026.

    In Fabricked, researchers from the same ETH Zurich group showed that a host controlling the hypervisor and UEFI firmware can misconfigure the Infinity Fabric interconnect so that the AMD Secure Processor initialises SEV-SNP incorrectly. On a Zen 5 EPYC processor this gave arbitrary reads and writes in the victim VM and forged attestation reports. AMD assigned CVE-2025-54510, rates it medium severity and reports platform firmware updates for its EPYC 7003, 8004, 9004 and 9005 server series, released in November and December 2025. ^{20 21 23 24}

    Demonstrated attack · Critical · Mitigated · Mechanism-class evidence. On the record

  • H100 attestation not bound to a specific confidential VM in TEE remote attestation for AI workloads

    The demonstration combines a genuine H100 report with forged Intel TDX evidence. It depends on the CPU attestation already being defeated; a GPU report alone does not demonstrate that an intact CPU-to-GPU trust chain was bypassed.

    The TEE.fail authors fetched genuine H100 confidential-computing attestations from a rented server running their TDX VM. They combined these with forged TDX quotes. A proxy running outside any TEE then passed both the TDX and the GPU attestation checks. The authors attribute this to NVIDIA not binding the H100 to the identities of specific VMs. Their site states more generally that NVIDIA's attestation reports are not bound to a specific confidential VM or CPU. Intel, AMD, NVIDIA and the affected deployments acknowledged the findings, according to the authors, and the affected deployments were working on mitigations. The attack does not target NVIDIA's confidential-computing components directly, so the authors state that there are no mitigations on the NVIDIA side. ¹⁴

    Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

  • Side channels and other attacks by the host on CPU and GPU TEEs in TEE remote attestation for AI workloads

    The cited studies concern particular CPU and GPU platforms and attack prerequisites. StackWarp has AMD microcode patches; the open class-level entry does not mean every cited defect is unmitigated or applies to every TEE-backed implementation.

    PAL*M and Attestable Audits cite published side-channel, single-stepping, interrupt-injection and memory-aliasing attacks on Intel TDX and AMD SEV, including T-Time, TDXploit, CIPHER-LEAKS, Heckler and BadRAM. PAL*M treats them as out of scope. Attestable Audits proposes revoking vulnerable enclave images. Gloria Z notes that performance counters have themselves been used as a side channel, for example in CounterSEVeillance. New attacks of this kind continue to appear. In StackWarp, researchers at CISPA showed that a malicious hypervisor can shift the stack pointer of an SEV-SNP guest on AMD Zen 1 to Zen 5 processors with simultaneous multithreading enabled, which fully breaks the guest's integrity. AMD released microcode patches. On the GPU side, an independent analysis of NVIDIA's confidential computing by IBM Research and Ohio State University found that bulk command and data transfers are protected, but some metadata, timing behaviour and coordination signals remain in unprotected shared memory. The authors report that these can reveal computational behaviour and in some cases allow manipulation of operations. They disclosed the findings to NVIDIA. ^{16 18 25 26 27}

    Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

  • Attestation covers launch state, and measurements can be incomplete in TEE remote attestation for AI workloads

    A general measurement-boundary limitation. The concrete WhatsApp configuration findings were fixed before launch; Apple's research-environment configuration flaw was also fixed. Their fixes do not remove the need to bind each deployment's runtime inputs.

    Attestation measures launch state, not runtime state. Data loaded later, such as model weights, must be bound separately. Gloria Z argues that gaps in measuring feature flags, environment variables and invocation arguments are "perhaps the most likely failure mode". She also warns that a badly designed hashing scheme could let two models with significantly different properties share a hash "without breaking the hash function itself". Independent reviews of production systems have found such gaps. In WhatsApp's deployment, Trail of Bits found environment variables and ACPI tables loaded outside the measurement, and rated both high severity. Meta fixed them. On an Apple PCC node running in Apple's research environment, a researcher reports that tampered configuration files left the attestation unchanged. ^{12 18 28 29 30}

    Theoretical argument · Significant · Open · Mechanism-class evidence. On the record

  • Deployment-level attestation does not cover the whole chip in TEE remote attestation for AI workloads

    A limitation of deployment-level evidence when the claim concerns all activity on a chip. It does not defeat a narrower claim about which software served one attested request.

    An attestation shows what one confidential VM runs. It does not show what else the hypervisor runs on the same hardware. Gloria Z calls the difference between deployment-level attestation and chip-wide monitoring "the gaping hole in this plan". This matters most for negative claims such as the absence of training. ¹⁸

    Theoretical argument · Significant · Open · Mechanism-class evidence. On the record

    Related mechanism R2 On-chip telemetry from timing, memory and performance counters: On-chip counters are a proposed route to evidence about everything a chip runs, which attestation of one workload does not give. A pointer, not evidence that this flaw is mitigated. Add

  • Root of trust concentrated in a few hardware vendors in TEE remote attestation for AI workloads

    Vendor trust is an assumption of the attestation chain. The root-seed extraction study concerns AMD EPYC Milan and firmware downgrade with privileged host and platform-flash access; it is not evidence of the same failure on Intel, NVIDIA or all AMD generations.

    The root of trust is the certificate authorities of a small number of vendors (AMD, Intel and NVIDIA), which generate the keys and fuse them onto the chips. Gloria Z notes that whoever has access to a hardware key, or can certify one, can in principle produce valid reports for arbitrary measurements without the physical chip. Attestable Audits notes that the approach holds only "as long as the vendor of the secure hardware is trusted". A 2026 preprint reports that a host with root control and the ability to rewrite platform flash can downgrade an AMD EPYC Milan processor to legacy security-processor firmware and extract the hardware root seed from which SEV-SNP attestation keys are derived. The authors state that this lets them forge attestation reports for any firmware version. AMD describes the firmware-loader flaw the attack starts from as a legacy attack mitigated in 2021. ^{18 25 31 32}

    Theoretical argument · Significant · Open · Mechanism-class evidence. On the record

Open significant flaws

5 flaws in 2 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Theoretical argument · Significant · Open. On the record

• Google Cloud attestation combines affected TEE components in Apple Private Cloud Compute

  An applicability question for PCC on Google Cloud, which uses Intel TDX. The cited attacks do not evaluate PCC's combined roots of trust, and do not attack its Apple-silicon deployment. A compromised TDX component alone does not establish a break of the complete PCC trust chain.

  Apple reports that PCC on Google Cloud uses Intel TDX, NVIDIA confidential computing and Titan. Components that could exfiltrate user data if compromised have at least two independent vendor roots of trust, and attested keys are held in a separate confidential VM. The TEE findings document physical-host TDX forgery and an H100 relay demonstration. Whether PCC's combined protections resist those attacks remains an open question. ^{10 14 15}

  Open question · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

Not yet demonstrated

R1 Chip location verification

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

The records connect no other mechanism to this proposal's gaps, open flaws or dependencies.

Blockers

6 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 33}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• TEE remote attestation for AI workloads
  • Published binaries cannot be rebuilt from source and carry no symbols, so checking what the attested software does needs reverse engineering. Evidence binding ¹¹
  • Outside developers can use PCC only with an entitlement from Apple, which is limited to small developers. Access & governance ³⁴

From the family or selected implementation's record. ?

Model weights

Not involved: Chip location verification.

Unspecified for TEE remote attestation for AI workloads. Check the implementation record.

Inputs and outputs

Not involved: Chip location verification.

Unspecified for TEE remote attestation for AI workloads. Check the implementation record.

Training data

Not involved: Chip location verification.

Unspecified for TEE remote attestation for AI workloads. Check the implementation record.

Chip location verification

• R1 Lucid sovereignty (location) certificates Standard, Lucid Computing

TEE remote attestation for AI workloads

• R3 Apple Private Cloud Compute Product
• R2 Attestable Audits Research prototype, University of Cambridge
• R2 Cove Open-source project
• R2 PAL*M Research prototype, University of Waterloo
• R3 Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Private Cloud Compute: A new frontier for AI privacy in the cloud, Apple Security Engineering and Architecture (SEAR) (2024). Original
9. Security research on Private Cloud Compute, Apple Security Engineering and Architecture (SEAR) (2024). Original
10. Expanding Private Cloud Compute, Apple Security Engineering and Architecture (SEAR) (2026). Original
11. Unlocking Apple's Private Cloud Compute: An Analysis of Privacy-Preserving Artificial Intelligence, Y. Dittmar et al. (2026). Original
12. Beyond Prompt Injection: Hacking Apple's Private Cloud Compute, D. Selmanaj (2026). Original
13. CVE-2026-20685 (Apple Private Cloud Compute Server Software), Apple (CVE Numbering Authority) (2026). Original
14. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
15. DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes, J. De Meulemeester et al. (2026). Original
16. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
17. A primer on secure enclaves, Tinfoil (2026). Original
18. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
19. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
20. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
21. Fabricked: Misconfiguring Infinity Fabric to Break AMD SEV-SNP, B. Schlüter et al. (2026). Original
22. WireTap: Breaking Server SGX via DRAM Bus Interposition, A. Seto et al. (2025). Original
23. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
24. SEV-SNP Routing Misconfiguration (AMD-SB-3034), AMD (2026). Original
25. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
26. StackWarp: Breaking AMD SEV-SNP Integrity via Deterministic Stack-Pointer Manipulation through the CPU's Stack Engine, R. Zhang et al. (2026). Original
27. Blueprint, Bootstrap, and Bridge: A Security Look at NVIDIA GPU Confidential Computing, Z. Gu et al. (2026). Original
28. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
29. What we learned about TEE security from auditing WhatsApp's Private Inference, Trail of Bits (2026). Original
30. Meta WhatsApp Private Processing (security review), Trail of Bits (2025). Original
31. Insecure Despite Proven Updated: Extracting the Root VCEK Seed on EPYC Milan via a Software-Only Attack, M. Shen & Y. Qin (2026). Original
32. MilanLaunchy Firmware Loader (AMD-SB-3045), AMD (2026). Original
33. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
34. Private Cloud Compute (Apple Developer), Apple (2026). Original