Proposal Explorer

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Chip location verification and Network taps and certifiers

No new hardware needed

Chip location verification and On-chip telemetry from timing, memory and performance counters

Failures since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ¹³

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip location verification: Analysis
• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Network taps and certifiers: Analysis

Open significant failures

8 failures in 3 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Known failure · Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Known failure · Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Known failure · Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ¹⁰

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{11 12}

  Known failure · Theoretical argument · Significant · Open. On the record

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{13 21}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Research demo Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this failure is mitigated. Add

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ¹⁷

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{8 10}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁸

  Scope limitation · Theoretical argument. On the record

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{14 22}

  Scope limitation · Open question. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ¹⁴

  Scope limitation · Open question. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ¹³

  Scope limitation · Open question. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this failure is mitigated. Add

Open questions

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁸

  Open question · Open question. On the record

Not yet demonstrated

Proposed Chip location verification and Proposed Network taps and certifiers

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  • Network taps and certifiers waits on it. Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
• Research demo Bounding unexplained information in outputs Add
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
• Research demo Tamper evidence for verifier devices Add
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Proposed Side-channel suppression for isolated facilities Add
  • Network taps and certifiers waits on it. Radio, power-line and thermal channels are not addressed by network-level designs.
• Operational use Sampled inference recomputation Add
  • Network taps and certifiers depends on it.
• Operational use TEE remote attestation for AI workloads Add
  • Chip location verification depends on it.
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Chip location verification and On-chip telemetry from timing, memory and performance counters Add
• Operational use Sampled inference recomputation needed by Network taps and certifiers Add
• Operational use Deterministic and bit-exact inference needed by Network taps and certifiers Add
• Research demo Tamper evidence for verifier devices needed by Network taps and certifiers Add
• Proposed Side-channel suppression for isolated facilities needed by Network taps and certifiers Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Chip location verification and On-chip telemetry from timing, memory and performance counters

Blockers

13 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 23}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{9 10}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{11 12}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁸
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ¹⁰
• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{22 24}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ¹³
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{13 15}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹³
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ¹³

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters and Network taps and certifiers.

Not involved: Chip location verification.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters and Network taps and certifiers.

Not involved: Chip location verification.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters and Network taps and certifiers.

Not involved: Chip location verification.

Chip location verification

• Proposed Lucid sovereignty (location) certificates Standard, Lucid Computing

On-chip telemetry from timing, memory and performance counters

None on the map

Network taps and certifiers

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
9. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
10. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
11. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
12. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
13. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
14. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
15. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
16. Verification Plan, R. Dean (2026). Original
17. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
18. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
19. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
20. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
21. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
22. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
23. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
24. Network Traffic Hashing, Amodo Design (2026). Original