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Built for an adversarial prover

Chip location verification and Tamper evidence for verifier devices

No new hardware needed

Chip location verification and On-chip telemetry from timing, memory and performance counters

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Chip location verification: Analysis
• On-chip telemetry from timing, memory and performance counters: Red-teamed

Open critical flaws

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{8 10}

  Theoretical argument · Critical · Open. On the record

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this flaw is mitigated. Add

Family findings

• Tamper evidence for verifier devices

  Context for AI 2040 inference-only verification stack. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • Seals are often defeated with simple methods in Tamper evidence for verifier devices

    Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor.

    In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones. ^{20 21}

    Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

  • Security depends on inspection protocols in Tamper evidence for verifier devices

    An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier.

    Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated. ^{21 22}

    Theoretical argument · Significant · Open · Mechanism-class evidence. On the record

  • Attack classes outside published models in Tamper evidence for verifier devices

    The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure.

    The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure. ^{23 24 25}

    Open question · Significant · Open · Mechanism-class evidence. On the record

Open significant flaws

10 flaws in 3 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Theoretical argument · Significant · Open. On the record

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ¹⁰

  Demonstrated attack · Significant · Open. On the record

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁸

  Theoretical argument · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{11 12}

  Theoretical argument · Significant · Open. On the record

• The recomputation server must be trusted in AI 2040 inference-only verification stack

  The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track. ^{13 14 16}

  Theoretical argument · Significant · Open. On the record

• Spare compute is not verified in AI 2040 inference-only verification stack

  The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs. ¹³

  Theoretical argument · Significant · Open. On the record

• A recomputation family degrades against prompt-controlling adversaries in AI 2040 inference-only verification stack

  The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving. ^{13 14 18 19}

  Demonstrated attack · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁸

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Chip location verification and R1 Tamper evidence for verifier devices

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open critical flaw “Software-read telemetry can be forged by the operator” in On-chip telemetry from timing, memory and performance counters. A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• R1 Memory wiping and proofs of secure erasure Add
  • Tamper evidence for verifier devices waits on it. Memory wiping may use existing algorithms, but hardware testing is at an early stage.
• R1 Network taps and certifiers Add
  • Tamper evidence for verifier devices waits on it. Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated.
• R1 Side-channel suppression for isolated facilities Add
  • Tamper evidence for verifier devices waits on it. There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist.
• R1 Whole-workload recomputation (reproducible packets) Add
  • Tamper evidence for verifier devices waits on it. A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
• R3 Sampled inference recomputation Add
  • Tamper evidence for verifier devices depends on it.
• R3 TEE remote attestation for AI workloads Add
  • Chip location verification depends on it.
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Chip location verification and On-chip telemetry from timing, memory and performance counters Add
• R3 Sampled inference recomputation needed by Tamper evidence for verifier devices Add
• R1 Whole-workload recomputation (reproducible packets) needed by Tamper evidence for verifier devices Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Chip location verification and On-chip telemetry from timing, memory and performance counters

Blockers

14 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 26}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{9 10}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{11 12}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁸
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ¹⁰
• Tamper evidence for verifier devices
  • A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. Performance & compatibility. Waits on Whole-workload recomputation (reproducible packets) ¹⁴
  • Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. Performance & compatibility. Waits on Network taps and certifiers ¹⁴
  • Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. Hardware trust. Waits on Tamper evidence for verifier devices ^{14 16}
  • There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹⁴
  • Memory wiping may use existing algorithms, but hardware testing is at an early stage. Coverage & hidden compute. Waits on Memory wiping and proofs of secure erasure ¹⁴
  • Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. Adversarial validation ^{14 16}

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Chip location verification.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Chip location verification.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Chip location verification.

Unspecified for Tamper evidence for verifier devices. Check the implementation record.

Chip location verification

• R1 Lucid sovereignty (location) certificates Standard, Lucid Computing

On-chip telemetry from timing, memory and performance counters

None on the map

Tamper evidence for verifier devices

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
9. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
10. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
11. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
12. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
13. Verification Plan, R. Dean (2026). Original
14. Get Involved in Verification, AI Futures Project (2026). Original
15. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). Original
16. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
17. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
18. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
19. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
20. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). Original
21. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). Original
22. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). Original
23. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). Original
24. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). Original
25. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). Original
26. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original