Proposal Explorer

Add claims to see which ones the mechanisms address.

In production

• R3 Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Memory wiping and proofs of secure erasure, Whole-workload recomputation (reproducible packets), Bandwidth limits and compartmentalization and Deterministic and bit-exact inference

No new hardware needed

Memory wiping and proofs of secure erasure and Deterministic and bit-exact inference

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Memory wiping and proofs of secure erasure: Analysis
• Bandwidth limits and compartmentalization: Analysis
• Deterministic and bit-exact inference: Analysis

Open significant flaws

10 flaws in 4 mechanisms

• Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

  Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. ^{5 6}

  Open question · Significant · Open. On the record

• Outside help during challenges in Memory wiping and proofs of secure erasure

  Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. ^{3 4}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R2 Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Spare compute is outside the scheme in Whole-workload recomputation (reproducible packets)

  The plan states that it does not verify that spare compute is not used for unapproved workloads, because this seems very challenging. Recomputation checks the correctness of declared work, not its completeness. ^{1 9}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Proofs of useful work for capacity accounting: Proposed as one input to accounting for spare capacity on declared hardware. A pointer, not evidence that this flaw is mitigated. Add

• Non-compliant work could be encoded inside compliant-looking packets in Whole-workload recomputation (reproducible packets)

  The plan notes that an AI company might try to encode a non-compliant workload inside a workload that looks compliant on the surface. ¹

  Theoretical argument · Significant · Open. On the record

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{14 17 18}

  Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ¹⁴

  Open question · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹⁶

  Theoretical argument · Significant · Open. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{19 21}

  Open question · Significant · Open. On the record

Open minor flaws

2 mechanisms with minor findings

• Gap between erased and total memory in Memory wiping and proofs of secure erasure

  Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. ³

  Theoretical argument · Minor · Open. On the record

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹⁹

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Memory wiping and proofs of secure erasure and R1 Whole-workload recomputation (reproducible packets)

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R2 Timed challenge-response and memory-occupation challenges Add
  • Bears on the open significant flaw “Outside help during challenges” in Memory wiping and proofs of secure erasure. Timed challenges bound how far away a helper can be by how quickly it must answer.
  • Memory wiping and proofs of secure erasure waits on it. Timed challenges must exclude remote memory and other helpers.
• R1 Proofs of useful work for capacity accounting Add
  • Bears on the open significant flaw “Spare compute is outside the scheme” in Whole-workload recomputation (reproducible packets). Proposed as one input to accounting for spare capacity on declared hardware.
• R2 Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• R1 Network taps and certifiers Add
  • Whole-workload recomputation (reproducible packets) waits on it. All traffic must reach the recomputation server via network taps, and the server's integrity is critical.
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.

Missing prerequisites

• R2 Timed challenge-response and memory-occupation challenges needed by Memory wiping and proofs of secure erasure Add
• R1 Network taps and certifiers needed by Whole-workload recomputation (reproducible packets) Add
• R2 Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Shared foundations

• Network taps and certifiers relied on by Whole-workload recomputation (reproducible packets) and Bandwidth limits and compartmentalization

Blockers

15 blockers recorded

• Memory wiping and proofs of secure erasure
  • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility ^{4 5 6}
  • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ^{3 4}
  • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute ⁵
• Whole-workload recomputation (reproducible packets)
  • Workloads are not reproducible by default, and achieving reproducibility may cost performance. Performance & compatibility. Waits on Deterministic and bit-exact inference ¹
  • Network packets are not individually reproducible by default; making them so may need considerable software, firmware and hardware work. Amodo rates this 'not on track'. Performance & compatibility ¹¹
  • All traffic must reach the recomputation server via network taps, and the server's integrity is critical. Hardware trust. Waits on Network taps and certifiers ^{1 11}
  • Recomputing training steps needs checkpoints: writing one at every step would cost more than 100% overhead, so Amodo's design needs a spare data-parallel replica that tracks the weights instead. Performance & compatibility ⁹
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ¹⁴
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ⁴
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{14 16}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{14 17 18}
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{20 22}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{19 23 29}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ¹¹
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{4 19}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Whole-workload recomputation (reproducible packets) and Deterministic and bit-exact inference.

Not involved: Memory wiping and proofs of secure erasure and Bandwidth limits and compartmentalization.

Inputs and outputs

Depends on the design for Whole-workload recomputation (reproducible packets) and Deterministic and bit-exact inference.

Not involved: Memory wiping and proofs of secure erasure and Bandwidth limits and compartmentalization.

Training data

Depends on the design for Whole-workload recomputation (reproducible packets).

Not involved: Memory wiping and proofs of secure erasure, Bandwidth limits and compartmentalization and Deterministic and bit-exact inference.

Memory wiping and proofs of secure erasure

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

Whole-workload recomputation (reproducible packets)

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

Bandwidth limits and compartmentalization

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Deterministic and bit-exact inference

• R2 Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• R3 Verde and RepOps (Gensyn) Product, Gensyn
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Verification Plan, R. Dean (2026). Original
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original
9. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
10. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
11. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
12. Get Involved in Verification, AI Futures Project (2026). Original
13. Proof-of-Learning is Currently More Broken Than You Think, C. Fang et al. (2023). Original
14. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
15. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
16. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
17. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
18. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
19. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
20. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
21. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
22. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
23. Batch Invariance (vLLM documentation), vLLM project (2026). Original
24. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
25. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
26. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
27. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
28. What is Delphi? (Delphi documentation), Gensyn (2026). Original
29. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original