Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Network taps and certifiers, Bounding unexplained information in outputs and Deterministic and bit-exact inference

No new hardware needed

Chip registries and manufacturing records and Deterministic and bit-exact inference

Failures since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ⁶

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip registries and manufacturing records: Analysis
• Network taps and certifiers: Analysis
• Bounding unexplained information in outputs: Independent red-team
• Deterministic and bit-exact inference: Analysis

Open significant failures

4 failures in 3 mechanisms

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ²

  Known failure · Theoretical argument · Significant · Open. On the record

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{6 14}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this failure is mitigated. In the proposal.

  Related mechanism Research demo Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this failure is mitigated. In the proposal.

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ¹⁰

  Known failure · Theoretical argument · Significant · Open. On the record

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{14 17}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this failure is mitigated. In the proposal.

Scope limitations

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{3 5}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ³

  Scope limitation · Theoretical argument. On the record

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{7 15}

  Scope limitation · Open question. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ⁷

  Scope limitation · Open question. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ⁶

  Scope limitation · Open question. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this failure is mitigated. Add

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{16 18}

  Scope limitation · Theoretical argument. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{8 17}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this failure is mitigated. Add

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹⁹

  Scope limitation · Open question. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{19 21}

  Scope limitation · Open question. On the record

Open questions

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ¹⁶

  Open question · Open question. On the record

Not yet demonstrated

Proposed Chip registries and manufacturing records and Proposed Network taps and certifiers

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Bandwidth limits and compartmentalization Add
  • Bounding unexplained information in outputs waits on it. The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound.
• Research demo Tamper evidence for verifier devices Add
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• Proposed Side-channel suppression for isolated facilities Add
  • Network taps and certifiers waits on it. Radio, power-line and thermal channels are not addressed by network-level designs.
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
• Operational use Sampled inference recomputation Add
  • Network taps and certifiers depends on it.
  • Bounding unexplained information in outputs depends on it.

Missing prerequisites

• Operational use Sampled inference recomputation needed by Network taps and certifiers and Bounding unexplained information in outputs Add
• Research demo Tamper evidence for verifier devices needed by Network taps and certifiers Add
• Proposed Side-channel suppression for isolated facilities needed by Network taps and certifiers and Bounding unexplained information in outputs Add
• Research demo Bandwidth limits and compartmentalization needed by Bounding unexplained information in outputs Add

Shared foundations

• Sampled inference recomputation relied on by Network taps and certifiers and Bounding unexplained information in outputs
• Deterministic and bit-exact inference relied on by Network taps and certifiers and Bounding unexplained information in outputs. In the proposal
• Side-channel suppression for isolated facilities relied on by Network taps and certifiers and Bounding unexplained information in outputs

Blockers

17 blockers recorded

• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{1 2}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{1 2 3}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{3 5}
• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{15 29}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ⁶
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{6 8}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ⁶
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ⁶
• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹⁶
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{8 17}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{8 14}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ¹⁶
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ¹⁶
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{20 22}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{19 23 30}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ³¹
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{8 19}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Network taps and certifiers, Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Not involved: Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for Network taps and certifiers, Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Not involved: Chip registries and manufacturing records.

Training data

Depends on the design for Network taps and certifiers.

Not involved: Chip registries and manufacturing records, Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Chip registries and manufacturing records

None on the map

Network taps and certifiers

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

Bounding unexplained information in outputs

None on the map

Deterministic and bit-exact inference

• Research demo Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• Operational use Verde and RepOps (Gensyn) Product, Gensyn
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
2. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
3. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
4. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
5. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
6. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
7. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
8. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
9. Verification Plan, R. Dean (2026). Original
10. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
11. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
12. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
13. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
14. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
15. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
16. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
17. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
18. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
19. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
20. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
21. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
22. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
23. Batch Invariance (vLLM documentation), vLLM project (2026). Original
24. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
25. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
26. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
27. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
28. What is Delphi? (Delphi documentation), Gensyn (2026). Original
29. Network Traffic Hashing, Amodo Design (2026). Original
30. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
31. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original