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Mechanism · Tamper evidence for verifier devices

Sources

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  1. BIBM Corporation (2012). IBM 4765 Cryptographic Coprocessor Security Module: Security Policy. NIST Cryptographic Module Validation Program. Source recordSupports: FIPS 140-2 Level 4; tamper-respondent matrix; sensed conditions; zeroization · Table 1; §2 physical security; §8.1 Table 9
  2. ANational Institute of Standards and Technology (2011). Cryptographic Module Validation Program Certificate #1505: IBM 4765 Cryptographic Coprocessor Security Module. NIST Cryptographic Module Validation Program. Source recordSupports: IBM 4765 validation date and historical certificate status · certificate page
  3. AJ. Obermaier & V. Immler (2018). The Past, Present, and Future of Physical Security Enclosures: From Battery-Backed Monitoring to PUF-Based Inherent Security and Beyond. Journal of Hardware and Systems Security. Source recordSupports: existence of a review spanning battery-backed to PUF-based enclosures · title and abstract (full text not read)
  4. AV. Immler et al. (2019). Secure Physical Enclosures from Covers with Tamper-Resistance. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019(1), 51–96. Source recordSupports: batteryless PUF cover design, attacker model, results, stated limitations, drawbacks of battery-backed enclosures · abstract; §2.1; §3.1; §8
  5. AP. Staat et al. (2022). Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems. 2022 IEEE Symposium on Security and Privacy. Source recordSupports: Anti-Tamper Radio concept, threat model, server experiment, costs, limitations · abstract; §III–§VI
  6. AM. S. Tabar et al. (2025). Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection. 18th ACM Conference on Security and Privacy in Wireless and Mobile Networks (WiSec 2025). Source recordSupports: signal-injection (compensation) attack on Anti-Tamper Radio under a known-reference model; RIS countermeasure · abstract; §3.1; §4.2.1
  7. BPHYSEC GmbH (2026). PHYSEC SEAL: Change detection for maximum safety. PHYSEC website. Source recordSupports: PHYSEC reports a commercial anti-tamper radio sensor for infrastructure enclosures · product page
  8. AT. Mosavirik et al. (2023). ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(1), 301–325. Source recordSupports: on-chip impedance sensing for tamper detection · abstract
  9. BH. A. Smartt & Z. N. Gastelum (2015). Tamper-Indicating Enclosures, A Current Survey. Sandia National Laboratories, SAND2015-4251C. Source recordSupports: tamper-indicating enclosures in verification regimes; approaches; limitations · abstract; survey sections
  10. BR. G. Johnston & A. R. E. Garcia (1996). Physical Security and Tamper-Indicating Devices. Los Alamos National Laboratory, LA-UR-96-3827. Source recordSupports: seal vulnerability assessment results; mean defeat time for one practised person · abstract; results; Table 2
  11. AR. G. Johnston (2001). Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials. The Nonproliferation Review, Spring 2001, pp. 102–114. Source recordSupports: high-tech vs low-tech seals; role of protocols and inspector training · main text
  12. BN. Cankaya (2026). A System Overview for Near-Term, Low-Trust AI Compute Verification. Machine Intelligence Research Institute. Source recordSupports: enclosure needs in low-trust AI verification; open question on retrofittable enclosures for side-channel defence; inspections · §2b; §4.2; §5.3.1
  13. CR. Dean (2026). Verification Plan. AI 2040. Source recordSupports: tamper-evident enclosures among physical security measures · physical security discussion
  14. BJ. Petrie et al. (2025). Flexible Hardware-Enabled Guarantees for AI Compute. arXiv. Source recordSupports: flexHEG secure enclosure for physical tamper protection · abstract

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